News vFinal DR 27/6/08 12:28 Page 7
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IMEC simplifies high-k
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metal gate process for high-tech,
high-quality
AT a VLSI Symposium, IMEC reports an dielectric high-k/metal gate CMOS, IMEC
improved performance for its planar increased the performance of nMOS and
components,
CMOS using hafnium based high-k pMOS transistors with 16% and 11%
dielectrics and tantalum based metal respectively. This results in an inverter
assemblies and
gates for the 32nm CMOS node. The delay improved from 15ps to 10ps. For
tailor-made systems
inverter delay advanced from 15ps to the first time, the compatibility of
10ps. IMEC also simplified its high- conventional stress memorisation
k/metal gate process by decreasing the techniques with high-k/metal gate has
number of process steps from 15 to 9. been demonstrated.
High performance (low Vt) high- Also, IMEC has simplified the process
k/metal gate CMOS has recently been complexity from dual metal / dual
achieved by applying a thin dielectric cap dielectric to single metal / dualdielectric
between the gate dielectric and metal by using soft mask processes and wet
gate. Both gate-first and gate-last removal chemistry. The process reduces
integration schemes have proven to be the complexity by 40% or 6 steps
successful. While the gate-last scheme is compared to dual metal / dual dielectric.
now introduced in production for high It also allows simpler gate etch profile
performance products, the gate-first control and it offers better prospects for
option remains attractive for low cost scaling. And IMEC proved that the use of
applications if its complexity can be La and Dy capping layers do not show any
reduced to the standard CMOS process reliability issues.
flow. One of the possibilities for gate first These results were obtained in
is a dual metal / dual dielectric process collaboration with IMECís sub 32nm
flow using mostly hard masks to pattern CMOS partners including Intel, Micron,
nMOS and pMOS regions selectively. Panasonic, Qimonda, Samsung, TSMC,
By applying conventional stress NXP, Elpida, Hynix, Powerchip, Infineon,
boosters to its gate-first dual metal / dual TI, ST Microelectronics.
Toshiba and IBM achieve higher
hole mobility
TOSHIBA CORPORATION announced bonding (DSB) wafers, a bulk CMOS
that, together with IBM Corporation, it hybrid type wafer that bonds and
has developed a higher performance substrates, is a recognised candidate for
CMOS FET, a high priority for advanced advancing this approach.
From planning
system LSI. The new technology In developing the new methodology,
matches the highest possible obtaining standard silicon wafers by
to production
performance, and opens the way for rotating the plane of the layer by 45
further advances in process technology. degrees and thinning the DSB layer of
High performance, low power and the substrate, Toshiba and IBM have
scalability have won CMOS technology a successfully integrated technology with
central place in semiconductor improving 10% delay of the ring
technology, a position now under threat oscillator than achievement compared to Oerlikon Mechatronics AG
as CMOS scaling edges towards conventional DSB substrate wafers. The
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fundamental physical limits that inhibit development improved the ring oscillator
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further advances in transistor delay to a point of 30% than the
CH-9477 Trübbach
performance and migration to finer standard wafers. The achievement can
Tel. +41 81 784 64 00
process technology. As a consequence, be integrated with technologies that can
Fax +41 81 784 64 01
the industry is seeking new ways to reach even higher advances.
overcome these challenges. These Toshiba and IBM achieved the
info.mechatronics@oerlikon.com
approaches include adoption of new performance using new hybrid
www.oerlikon.com/mechatronics
materials such as high k and metal orientation technology fabricated on a
gates and new structures. Another way hybrid substrate with different crystal
to improve performance is to increase orientations to achieve significant PFET
the mobility of electron , or holes, performance improvement without any
through device channels; direct silicon deterioration in NFET performance.
July 2008
www.euroasiasemiconductor.com
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