EVG vFinal DR 27/6/08 12:46 Page 16
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WAFER BONDING
Wafer Bonding for 300 mm
3D Integration
The semiconductor industry has traditionally
Given these advantages, then, it’s not surprising
that the first market to drive widespread demand
gained improvements by scaling down but as the for wafer level 3D packaging is CMOS image
industry moves towards atomic structures there
sensors (CISs) for the cameras now housed in
virtually every cell phone. As camera resolution
has been improvements achieved by improving continues to improve, the CIS takes up more
integration processes. Markus Wimplinger,
valuable real estate in the phone, heightening,
amongst other reasons like increased quality and
Director of Business Unit Technology Development cost demands, the need for TSVs and serving as
and IP at EV Group discusses how demand for
the primary short term driver for ramping up TSV
production.
TSVs has driven wafer bonding to 300mm Memory devices are expected to drive TSVs into
true high volume production, beginning this year
with flash memories and adding SRAMs and
DRAMs by 2010, according to market research
W
firm Yole Développement (Lyon, France). Logic
devices will take a bit longer to make the transition
hile through silicon vias since technical requirements for their packaging,
(TSVs) for 3D packaging and hence for TSVs, will be more stringent. Figure
applications have been in 1 provides Yole’s assessment of when TSV
development for some time, technology node structures will be required for various device types.
shrinks and device integration are combining to The emerging shift to volume manufacturing of
compel deployment of TSVs in volume production. TSVs is also the catalyst for wafer bonding to
Because TSVs enable shorter interconnects make the switch to 300 mm technology. Although
between device components, signal speed and currently CIS packaging is still performed mainly
parasitic power consumption can be greatly on 200 mm wafers, transition to 300 mm
improved. In addition, because they contribute to manufacturing is expected for future high volume
overall reduction in package size and footprint, manufacturing of CIS packages. EV Group was the
Figure 1. (Source: TSVs are ideal for use in end products where space first to market with 300 mm fully automated
Yole Développement) is at a premium. silicon on insulator (SOI) wafer bonders in 2001,
and with semi automated high pressure and high
temperature bonders in 2002. Today, given the
aforementioned market forces and 300 mm
roadmaps, Yole predicts that 36 percent of all 3D
wafers processed in 2008 will be 300 mm and
more than 80 percent by 2012, EVG is leveraging
this market and technology leadership with its
latest wafer bonder. The 300 mm EVG560 high
pressure, high temperature production bonding
platform was designed specifically to accommodate
the growing use of wafer bonding in such
applications as 3D stacking of DRAM and flash
memories with TSV technology, CIS packaging,
and backside illuminated CISs.
Shrinking the CIS
In current generation cell phones, the camera is
the thickest part; in fact, on flip phones, it’s
typically mounted inside the hinge in an effort to
www.euroasiasemiconductor.com July 2008
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