EVG vFinal DR 27/6/08 12:46 Page 17
WAFER BONDING
17
manufacturing technologies. However, market pull
from systems integrators like Nokia pushed the
There are
supply chain to come with new package technology
and processes that could be easily adopted. The
some very
availability of production level equipment for 300
mm wafer sizes, bonders, spray coaters, double
specific
side aligners, combined with optimisation for 3D
steps for 3D
TSV, came together over the last three years to
fulfill the roadmap requirements for high volume processing,
TSV manufacturing.
including
Solution for 300 mm 3D
double side
wafer bonding
There are some very specific steps for 3D lithography,
processing, including double side lithography, the
need to do precise alignment to create TSVs,
the need to
actual TSV processing, thin wafer handling, and of
do precise
course, wafer bonding or chip to wafer bonding.
CIS manufacturing at the wafer level consists of a
alignment to
stack of lens wafers and spacer wafers, and of
create TSVs,
course the CMOS image wafer containing the
TSVs. In some cases, such as backside illuminated
actual TSV
image sensors, this wafer already consists of a
bonded stack.
processing,
The wafer bonder’s use can be tailored to the
thin wafer
manufacturer’s specific requirements. Wafer
bonding processes function based on temperature handling,
and applied pressure/force, using specific
Figure 2. (Source EV Group) adhesives, process sequences, etc., and the bonder
and of
itself can be used for a wide variety of bonding
course,
processes. Wafer bonding for 3D integration has
minimise impact on footprint. Employing TSVs the potential to be applied to any chip that goes wafer
enables the image sensor thickness to be greatly into handheld devices, particularly with respect to
reduced and allows more flexibility in the overall the issue of power consumption. If the
bonding or
size and design of the phone. It also simplifies the interconnects are more efficient and consume less
chip to
packaging process, because the connections can be power, the cell phone’s battery will last longer, a
routed to the backside of the CIS, the bond pads ubiquitous concern on the part of consumers.
wafer
needn’t all be located on front side, which can thus The EVG560, shown in Figure 3, was
bonding
be fully encapsulated with a glass layer. Figure 2 specifically developed for these kinds of
shows an example of a wafer level camera with applications. The field proven modules used in the
TSVs. system were first installed in the field for industrial
Moreover, new generation CISs will feature R&D in 2002 and subsequently evolved into
optics that can be fully integrated on the front side production use. The aligner that goes with the
in a wafer level format, making it even more bonder has been field proven for some time as well.
advantageous to route all connections to the The multiple chamber bonder is 300 mm ready,
backside. This further simplifies CIS package handling is performed using a robot, and all
development and assembly because it enables the interfaces are fully compatible with 300 mm
image sensor to be mounted with other chips in a standards, including the front opening unified pod
standard reflow process using standard (FOUP) interface, the software interface with
temperatures. Previously, a separate process was factory automation used in 300 mm fabs, and
required, as the optics couldn’t survive the high wafer ID readers. However, the bonder’s ability to
temperatures required to solder chips onto the handle both 300 mm and 200 mm glass and silicon
board, pointing up the cost effectiveness of wafers, simultaneously, if desired, enables its use
implementing TSV/3D integration for CIS devices. as a bridge tool for transitioning to 300 mm
Indeed, the costs associated with TSVs have production. In addition, the fully automated system
been the primary roadblock to their use in is process compatible with EVG’s manual and semi
production up to now, reinforcing customers’ automated bonding systems, further facilitating
typical reluctance to pursue adoption of new implementation of volume production.
July 2008
www.euroasiasemiconductor.com
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