p22-24 EAS IC Awards materials 1/7/08 14:11 Page 24
24 IC INDUSTRY AWARDS PREVIEW
MATERIALS IMPROVEMENT AWARD
DUPONT/EKC TECHNOLOGY
need for endpoint detection. The 8500 traced back to the starting material, and
www.ekctech.com can be used to simplify planarisation in particular to the metal impurities in
processes that employ reverse-mask the active layer. The active layer has no
Copper/low-k post-etch residue etchback steps. This slurry contains gettering sites, and the buried oxide in a
remover chemistries that exhibit topography- BSOI structure prevents diffusion of most
dependent polishing behaviour that coat transition metal impurities out of the
The CuSolve EKC520 copper/low-k post- the wafer surface to automatically stop active region into the bulk or the back
etch residue remover is a rapid, single- polishing when the topography has been surface of the wafer where the gettering
wafer cleaning solution for copper removed. The slurry removes oxide sites are normally formed. To find a
interconnect post-etch residue and copper topography (“Up” oxide) of up to solution that is layout-independent, a thin
oxide removal. It effectively removes 20,000A in step height with very little polysilicon layer was added between the
residues from via first/trench last and removal of the oxide at the bottom of active silicon layer and the buried oxide
trench first/via last structures; works with trenches (“Down” oxide) for high layer. Gettering efficiency was estimated
single and dual damascene processes; and planarization efficiencies throughout the based on DLTS measurement of iron (Fe)
is compactible with copper, barrier, and polish. SureStop 8500 provides step concentration in the active region after
low-k films, and all single-wafers tools. height removal of>5000A/min and intentional contamination of BSOI wafers.
The product reportedly meets particle blanket removal rates of <300A/min. A thin polysilicon layer in a BSOI wafer
performance requirements for advanced reduces the Fe concentration below the
technologies, in water soluble, and can be detection limit 1E+11 at/cm3, compared
disposed of in aqueous disposal drains. No to 1.9E+13 at/cm3 in a standard BSOI
post-clean rinse other than water is wafer, implying gettering efficiency >
required. RC delay reductions of up to 7% 99%. The result is independent of the
have reportedly been achieved at a major
OKMETIC OYJ
polysilicon film thickness from 0.2 µm. to
copper foundry. DI water savings of >1.2
www.vtt.fi 1.0 µm.
million gallons/month, or >15.2 million A high temperature process simulation
gallons/year can be realised using an G-SOI - gettered SOI substrates for was carried out based on a process cycle
EKC520 process for a wafer fab running integrated MEMS and CMOS with 24h at > 1000°C, and a maximum
single-wafer tools on 65nm devices (10 processes temperature 1150°C for 4 h. The
levels of metal, 2 cleans per level). gettering efficiency analysed after the
Okmetic has developed a new thick BSOI high temperature processing of wafers
ENTEGRIS
product with built-in gettering properties was > 97%. The buried polysilicon layer
www.entegris.com. (G-SOI). The wafer is designed for solves the gettering problem for metal
integrated MEMS and CMOS processes. impurities in bonded SOI wafers for
The Ultrapak Edge Guard The gettering effect is achieved by a integrated MEMS and CMOS processes
buried polysilicon layer between the active where SOI is required for the realisation
The Ultrapak Edge Guard 200mm wafer layer and the buried oxide of a BSOI of the sensor element. Testing of wafers in
shipping box is said to reduce edge structure. The push towards G-SOI CMOS processes show clearly better gate
contamination, with 50% or more product development came from a gate oxide integrity than in standard BSOI
reduction in particle contamination from oxide integrity problem that was wafers, and in fact it is as good as in
edge contact. This is expected to prevent encountered when CMOS processes were conventional bulk silicon wafers.
particle-induced device defects during implemented on standard thick BSOI The wafer is designed for integrated
circuit fabrication. Designed for re-use, wafers. It took the form of midfield MEMS and CMOS processes where the
the shippers have horizontal and vertical breakdown sites while testing the gate SOI is required for realisation of the
robotic pick-up flanges on the cassette, oxide breakdown voltage, for example. sensor element. It can also be used in
while centre notch track alignment and The occurrence of gate oxide failure was bipolar/BiCMOS applications
H-bar features ensure accurate equipment
interoperability.
FERRO CORPORATION
www.ferro.com
Self-stopping CMP slurry
The SureStop 8500 self-stopping
chemical mechanical planarisation slurry
for inner layer dielectric materials
provides a reported planarisation
efficiency of >95% with an increased
over-polish window and eliminates the
www.euroasiasemiconductor.com July 2008
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