XSIL vFinal DR 30/6/08 16:51 Page 15
COVER STORY
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overburden becomes critical only for
thickness of metal layer >~1-2µm. Rapid
progress shown recently in
commercialisation of DPSS and fibre
lasers of ps and sub ps pulse width
permits suppression of residual
overburden by reduction of thermal
diffusion length. Reliability of short pulse
width lasers is now increasingly
approaching that of standard industrial Q-
switched lasers. Sometimes Via etching
on the back grinded side of Si wafer is
needed while polished surface is attached
to another substrate. However, particles Fig.10 Unpolished wafer by optical microscope -a, debris on protective coating
and contaminations on rough Si substrate after machining –b, coating and debris washed – c, resulting Via close-up – d
create problems for RIE such as plasma
arcing in reaction chambers. In contrast
laser process demonstrates a good quality photolithography steps, increasing expensive wafer fabrication process such
(Fig.10). throughput, and providing a platform as photolithography, RIE, CVD and
for simplified seed deposition and IPVD.
Conclusions accelerated electroplating. It has
Laser Via machining is an enabling also been shown to be a stress free
technology for front and back end TSV process, safe for active devices, having This article was presented as a paper at
interconnect applications providing reliable operation and inexpensive the IMAPS 4th International
reduced CoO by eliminating the maintenance costs. Laser drilling aims to Conference and Exhibition on Device
requirement for expensive reduce fabrication costs by bypassing Packaging 2008
REFERENCES:
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Processing in Microelectronics and Photonics, San Jose, USA, Science, Vol.186, pp.288-292, 2002.
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[2] D.Perrottet, B.Diggin, B.Farrell, “Laser-Based Dicing: Doing in Crater Properties During High Power Nanosecond Laser
Thin Better”, EuroAsia Semiconductor Magazine, Vol.29, N.6, Ablation in Silicon”, J.Appl.Phys., Vol.88, N.3, pp.1638-1649,
pp.17-20, July, 2007. August, 2000.
[3] “Xsil is Developing New Solutions for TSV applications” in [12] R.Nagarajan, K.Prasad, L.Ebin, B. Narayanan,
Micronews, 3D IC & TSV Packaging Newsletter, N.2, p.3-4, “Development of dual-etch via tapering process for through-
December, 2007. silicon interconnection”, Sensors and Actuators A: Physical,
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Components and Technology Conference, pp.1367-1374, June, J.M.Swan, “Fabrication and Electrical Characterization of 3D
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[8] A.C.Forsman, E.H.Lundgren, A.L.Dodell, A.M.Komashko, [16] S.Vitkavage, “Through Silicon Vias: Building a Bridge
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July 2008
www.euroasiasemiconductor.com
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