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IC INDUSTRY AWARDS PREVIEW 23
reactions depending on the nature of the verifying that newly created microchips to successfully
molecular precursor. In any case, the meet lifetime and performance integrate a VLG
electro-initiated nucleation secures the requirements. During the burn-in process, structure in a
growth of the film in a conformal and sample chips are subjected to extreme 0.18um and below
uniform manner. Through controlling just heat. Burn-in materials are used to image sensor structure
the current, Alchimer is able to transfer that heat to the chip for the test. and compatible with both Al
demonstrate the deposition of ultra thin Traditional materials that have been used and Cu backend. Unlike conventional
films of less than 10nm, with high for this application provide good thermal approaches, the resulting optical stack is
uniformity across surfaces over a broad performance, but their use is limited to a not diffraction-limited.Excellent planarity
range of substrate resistivities. single cycle and a residue is typically left above the optical elements was achieved,
One of the first applications of behind that must be cleaned before the eliminating the potential need for CMP,
electrografting technology is copper seed next test. Honeywell's material eliminates and dark current performance was not
layers in TSV metallization. eG ViaCoat the cleaning step and, since it can be used compromised.
has the unique ability to enable ultra-thin repeatedly, reduces material usage. The Silecs has likewise demonstrated the
and conformal copper seed layer new material also has superior effectiveness of the second technique,
deposition in the 50 to 500nm range, a performance to alternative multi-use using low RI SC500 as a topcoat. The
major roadblock to 3D packaging thermal interface materials used for burn- glass-like behaviour of this SOD material
adoption due to the dry vacuum processes in. Besides the described application as a offers the advantage of micro lens
in use for the past 40 years. This process burn-in material, Honeywell's material protection during sawing and improves
can easily be implemented using industry- can also be used in a broad spectrum of epoxy base-like packaging compatibility.
standard copper electroplating equipment, processes as a thermal interface material The SOD was engineered to enable
removing any requirement for additional (TIM) for thermal modules or assembled excellent planarity or conformality above
capital expenditure. packages. micro lens array with superior film
PVD (physical vapor deposition) quality. The use of a low refractive index
processes have already reached their topcoat enables focal lengths in the
limitations in terms of producing intermediate range (between backend
continuous layers for through silicon vias without topcoat and backend with a
with aspect ratios of 3:1 and above. In common organic topcoat).
practice, this is a major roadblock to the The technique introduces an extra
adoption of advanced 3D packaging. degree of freedom in the design of optical
Alchimer's electrografting process using system focal length through control of the
eG ViaCoat demonstrates conformal SOD bake conditions. When the focal
sidewall and bottom coverage even on length is kept the same for an existing
highly scalloped TSV etch profiles, and at
SILECS, INC.
integration scheme with or without
aggressive TSV aspect ratios. Reliable wwwsilecs.com topcoat, the same optical performance is
metallization of TSVs with aspect ratios obtained. This is achieved by adjustment
of 13:1 is now possible. New use of spin-on dielectric of micro lens height for each case. Again,
eG ViaCoat enables significant materials to enable new generation of there is no degradation in dark current
reductions in cost of ownership (CoO) CMOS sensors performance.
compared to dry vacuum processes. For The two integration schemes (VLG and
example, for 10:1 aspect ratio TSVs, the Increasing the performance requirements lens topcoat) are complementary, and
CoO of Alchimer's electrografting process in CMOS image sensors (CIS) for digital used in combination, enabling a new
is 85% less than that of a traditional cameras is driving a need for generation of more efficient, sensitive and
PVD process. The cost advantage improvements in both the optical portion reliable CMOS sensors that have a
increases further at higher aspect ratios of CIS devices and the durability of the smaller footprint. The work, conducted at
and electrografting can be applied using camera module assembly. Silecs' state-of-the-art production facility
industry-standard copper electroplating Enabling materials innovator, Silecs, has in Espoo, Finland. Silecs' advanced
equipment, eliminating new capital developed two novel uses of Spin-on enabling materials are developed and
expenditure. Dielectric (SOD) materials to accomplish manufactured in semiconductor-like
both of these objectives. Each of the new clean-room conditions, mirroring the
approaches uses SOD in the construction production environments of the company's
of the optical stack, in contrast to the microelectronics manufacturing
organic photo resist-like materials customers. Process represents a unique
conventionally employed. In the first new way to use spin-on dielectric
method, a vertical light guide (VLG) materials; process resulted in significant
HONEYWELL ELECTRONIC
structure is formed in the device backend performance improvements; process
MATERIAL
and filled with high refractive index SOD enables a new generation of more
www.honeywell.com (RI=1.65 @ 633nm) to improve optical efficient, sensitive and reliable CMOS
performance. The second method sensors with a smaller footprint. Work
Reusable Thermal Interface Materials employs a low refractive index SOD was conducted with leading customer in
(RI~1.28 @633nm) topcoat, which Silecs' state-of-the-art mfg facility in
This material provides, repeatable enables easier micro lens engineering and Espoo, Finland with production conditions
thermal performance over many optimisation, and also offers the that mirror microelectronics\' clean-room
thousands of test cycles. The material is advantage of protecting the organic micro environments. Silecs is a thriving
used during the semiconductor burn-in lens with a glass-like layer. emerging player in the highly competitive
testing process, which is a critical step in Silecs has applied the VLG technique electronic materials industry.
July 2008 www.euroasiasemiconductor.com
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