XSIL vFinal DR 30/6/08 16:51 Page 13
COVER STORY
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size and the V density. Drill rates for the
X300V-Ultra production tool vary for the
different products from, for example,
17,000Vias/min for a 300mm wafer
comprising 657 dies with 100 Vias per
die of 20µm diameter and 60µm depth up
to >53,000Vias/min for a similar wafer
with 1000 Vias of 15µm diameter and
50µm depth per die, 657,000 Vias per Fig.8 Via of ~5µm diameter laser drilled in Si: top view and cross section
wafer. Corresponding throughput is rated
at 15 wafers/hour for the first example Optimal taper angles for techniques employed to address the
cited and 4-5 wafers/hour for the latter. Via metallisation problem of tapered sidewalls with Bosch
Besides greater ablation efficiency, Physical Vapour Deposition (PVD) is a DRIE by subsequent isotropic etch [12]
available with current UV laser systems, low temperature technique adopted for also smooth the scallops.
the high drilling rates have been barrier and seed layer deposition used to In contrast to the DRIE approach to
facilitated by the progress in the both insulate Via sidewalls prior to Via generation the laser process reported
development of rapid scanning metalisation and promote adhesion during here enables rapid machining of high
galvanometers providing reduced settling and subsequent to metalisation. quality Vias with sidewalls tapered at
times at the higher jump speeds used to However, the technique does not optimal 85° angles, considerably
move between Vias. Further advances are appear to be suited to the Via sidewalls simplifying and accelerating
anticipated in the product roadmap which which are typically produced by DRIE metallisation. Taper angles of laser
will enhance the throughput by >50% processes where scalloping seems to be processed Vias such as those displayed in
within the next 2-4 years. currently inherent in processes with Fig.5, approach the optimal value for void
acceptable throughput. Alternative free Cu plating and can, in turn, eliminate
Sidewall quality at high techniques, such as Chemical Vapour the need for ion assistance during the
ablation rates Deposition (CVD), tend to produce Vias PVD process.
Sidewall quality is widely regarded as whose metalised interconnects suffer from These properties alone make laser
being crucial for TSV interconnects weak adhesion to the sidewall and which drilled Vias attractive for any TSV
applications to permit efficient and results in low yield subsequent to wire interconnect application.
effective metallizsation. Any bonding. High aspect ratio Vias with Incorporated cleaning
imperfections can potentially occlude straight sidewalls are also a challenge for process
regions of the sidewall during the coating conformal sputtering and void free The laser process being a form of drilling
process resulting in a defective Via with electroplating. Ion assisted PVD is an unavoidably produces particulate matter
adhesion and or continuity issues. expensive solution to address this
Certain DRIE processes suffer from such problem.
an artefact where sharp, regular scallops, It is known that a tapered Via ensures
produced due to the interplay of conformal seed and simplifies Cu filling
The restrictions
mask/etch steps in a narrow closed by reducing the effective aspect ratio
channel like a Via, give rise of inter [13]. A tapered Via profile is therefore imposed by the DRIE
Via electrical leakage current [12] preferred over the vertical for barrier,
and increase the risk of dielectric seed layer deposition and rapid plating
process do not easily
breakdown. [13]. The form factor does not suffer
lend themselves to
The optimised laser process developed since the bottom diameter remains
at Xsil ensures smooth sidewalls on unchanged and an insignificant fraction of resolving the taper
silicon wafers. From the examples of Fig. interconnects densities are sacrificed. The
5 it can be seen that smooth Via sidewalls restrictions imposed by the DRIE process
and scalloping
are obtained that enable straightforward do not easily lend themselves to resolving
issue, which are
metalisation. the taper and scalloping issue, which are
Surface roughness figures of ~0.12µm inherent in certain DRIE processes
inherent in certain
have been measured on a Zygo White without adversely affecting the throughput
DRIE processes
Light Interferometer of Vias which were [12]. This is especially so in cases where
processed at removal rates as high as attempts are made to maintain uniformity
without adversely
~20µm/shot. of Via depth and quality over 300mm
This roughness value is associated only wafers. Attempts to compensate for the
affecting the
with occasional large scale irregularities inherent difficulties have only limited
throughput
of condensed Si while fine structure is not success yielding Vias with tapers limited
visible optically giving the surface a to a few degrees that tend to straighten at
polished appearance. relatively small aspect ratios. Dual etch
July 2008
www.euroasiasemiconductor.com
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