News vFinal DR 27/6/08 12:29 Page 10
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NEWS DESK
SRC tames
nanotubes
SEMICONDUCTOR RESEARCH
CORPORATION (SRC), a university
research consortium for semiconductors
and related technologies, joined with
researchers at Stanford University to
announce multiple ‘firsts’ demonstrated
with carbon nanotubes (CNTs) to produce
CMOS compatible working circuits on a
wafer scale. CNT Field Effect Transistors
(FETs) are considered contenders for
extending current CMOS technology to
create higher level chip capability.
The research is funded by the Focus
Centre Research Program (FCRP), a
subsidiary of SRC. Efforts to perfect CNT
technology to the point necessary to be
considered for affordable and practical
application in computer chips have been
underway since the first CNT transistor
was demonstrated one decade ago.The
accomplishments are rooted in the
Stanford team’s invention of a design
technique that creates logic cells which
function correctly even in the presence of
mispositioned CNTs.
“At the nanoscale, it’s nearly
Integrity.
impossible to guarantee that all carbon
nanotubes will be placed at correct
positions and aligned to create a
functional circuit. So the question is: if
When your
we can’t control these layout
requirements, how can we create working
circuits?” noted Betsy Weitzman, director
employees wear it,
of FCRP. “This exciting research has
brought forward a significant
breakthrough for the application of CNTs
your product has it.
in CMOS circuits; very efficient and
effective design solutions that don’t
require super precise placement of the
CNTs. The Stanford researchers developed
an inexpensive design flow that is
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www.euroasiasemiconductor.com July 2008
8213 PFG-EuroAsia.Grid.indd 1 3/26/08 10:51:14 AM
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