Metrology
Issue IV 2009
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41
Listening to low-k
layers
O
ne of the more challenging
defects encountered
during chip fabrication is
cracking of the low-k interlayer dielectric (ILD)
Semiconductor manufacturing is used to
material that is placed between layers of
discovering challenges as processes and
metallization. The ILD has played a vital role in
moving to smaller design rules by solving
materials are introduced to the manufacturing
problems involving power, crosstalk and signal
line. The layers of materials required for low-k
transmission, but the numerous materials used
to form the ILD have a nanoporous structure
and metallization are one example as they that makes them structurally weak and
tend towards fragility in manufacturing.
susceptible to cracking.
The materials themselves may be spun or
Tom Adams, a consultant with Sonoscan, evaporated onto the wafer. Most are spun on,
discusses a method using acoustic micro
generally at a temperature ranging from 200°C
to 250°C. Both spun-on and evaporated ILDs
imaging to locate vertical cracks in the inter are susceptible to cracking, which is sometimes
layer dielectric material that could dramatically
caused by differences in the coefficient of
thermal expansion (CTE) between the ILD and
speed the search for such defects. adjacent layers. Overall, ILDs that are
evaporated onto the wafer are probably
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