IC Industry Awards Preview 2009
SOKUDO
chip die is underfilled using a special with the competing configuration known
RF3T Coat/Develop System
fine fillet underfilling process. The ISM is as fcPoP, such as warpage management
inverted and attached to the top surface and SMT process difficulties associated
of the Flip Chip device leaving exposed with mounting the PoP top and bottom
The RF3T system, the company’s highest bond fingers for subsequent wirebond packages.
productivity, lowest cost-of-ownership interconnection to the base substrate.
(CoO) coat/develop track system The wirebondable bare die is attached
targeted for the full range of lithography onto the top surface of the ISM-LGA.
Surfect Technologies
applications. This system extends the Finally both the ISM-LGA and bare die
capabilities of SOKUDO’s established are wirebonded to a common base
Ascent 200
RF3 platform to achieve 200 wafer per substrate. This is followed by a single
hour (wph) throughput, keeping pace step overmolding process. Surfect Technologies has launched two
with the fastest lithography scanners new development electroplating tool
while maintaining process transparency. A typical fcPiP integrates an ASIC or versions that leverage its Ascent 200mm
DSP logic device (generally with flip and Leapfrog 300mm scalable plating
To achieve a 10% throughput chip interconnection) with memory die(s) tool platforms. These new development
improvement over the RF3S, the RF3T (in the ISM configuration) and analog tools are designed to enable more
system features additional parallel die(s) (in bare die configuration), the companies to enter and support the
process modules and higher efficiency latter two interconnected to the growing market for wafer level
wafer transport. The develop cell has common substrate using wire bond packaging by providing the basic metal
been reconfigured for eight develop interconnection. A typical package could deposition engines along with control
modules in the same platform footprint have a footprint of 15x15 mm, 1.4mm and chemical delivery systems.
to provide 60% higher develop and maximum thickness and incorporate a
rinse process capability than the 0.5 or 0.4mm ball pitch. Surfect’s tool offerings are built around
previous system. the industry’s only one-chamber plating
3D packaging is driven by wireless and tool, which rapidly scales through well-
A novel wafer coating dispense system consumer products that require package known copy-exact manufacturing
significantly reduces chemical level functional integration in the methods to optimize both low-volume
32
consumption, the largest contributor to smallest footprint, lowest profile and and high-volume plating solutions in the
track operating cost. Combined, these lowest cost. Stacked die packages for smallest space.
www
features provide lower CoO and higher Flash, SRAM and DRAM memories in an
.eur process performance for lithography FBGA package footprint using wirebond Surfect’s tool is unique in that it
oasiasemiconductor
applications. interconnection are widely available combines traditional single-bath,
today. multiple-tank plating approaches into a
single-cell process with software recipe
However, with the onset of more control of all metal deposition - all in a
complex device designs, two new small footprint. The plating computer’s
The IC Industry Awards
challenges have arisen: (a) higher I/O sensors enable accurate real-time
will be presented at
.com
density and performance requirements monitoring and control while providing a
SEMICON Europa 2009
on logic chips dictate the use of flip chip development architecture to add
interconnection, and (b) the complexity statistical and chemistry monitoring
square4
Issue IV 2009
of memory chips makes it difficult to routines. Surfect is also developing and
STATS ChipPAC
obtain them in “known good die (KGD)” offering a library of process solutions
Flip Chip Package-in-
form. enabling more complete wafer level
Package (fcPiP)
interconnect solutions
fcPiP addresses these concerns: the use
of flip chip interconnection for the logic
die addresses the need for high I/O
Ziptronix, Inc.
STATS ChipPAC’s Flip Chip Package-in- density and low parasitics, while the
Package (fcPiP) is an innovative family of procurement of memory in the form of
Direct Bond Interconnect
3D packages that stack minimally pre-tested ISM packages ensures that
Technology
packaged die and bare die into a single the memory devices are “known good.”
molded package. An additional benefit is the high level of Ziptronix's patented Direct Bond
reliability made possible by the Interconnect (DBI(r)) technology
A pre-tested Internal Stacking Module overmolded structure which is typically provides a solution to the challenge of
(ISM) Land Grid Array (LGA) and one or superior to flip chip–only packages. economical 3D integration of
more bare die are stacked with at least advanced semiconductors. DBI enables
one bare die connected to the substrate In addition, the fcPiP configuration reliable, repeatable, low cost
using flip chip interconnection. The flip obviates certain problems associated wafer-to-wafer or chip-to-wafer bonding
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