IC Industry Awards Preview 2009
Wafer Processing FEOL Award
DESCRIPTION
The processing of a wafer to create microelectronic devices involves a
number of highly complex and technical steps to achieve the devices that
drive the electronics industry. As important as each step is, it is the
integration of all these processes that determines the outcome of the
manufacturing process.
The processing requires diffusion, bake, lithography, etch, implant, clean,
as well as all the ancillary processes and support to create the desired
outcome. Once the tool sets are in, it is the creative approaches of the
engineers that ensure constant creative leaps.
WAFER PROCESSING - FEOL AWARD
This Award is for the product or process that enhances the manufacturing
process at the Front End Of Line and enables manufacturers develop
solutions to the increasing challenges at this point of manufacturing
Intevac
capability claims superior etch process
Lean Etch’ platform
control, a large process window; higher
etch rates, a continuous vertical profile
28
ntevac’s Lean Etch claims the first ever and high PR selectivity.
wafer processing system built with lean
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principles. The Lean Etch system’s
.eur
Applied Materials, Inc
parallel architecture utilises two sets of
Lam Research Corporation
oasiasemiconductor
BLOk II PECVD
twin linear robots to replace the large,
central handler commonly found on all
2300 Motif
The Applied Producer BLOk (Barrier cluster tools. The linear platform
Low k) PECVD (Plasma-Enhanced eliminates dependency on a single, The 2300 Motif post-lithography pattern
Chemical Vapor Deposition) system central handler and enables faster wafer enhancement system is designed for
provides ultra low k copper barrier and transport and higher space utilisation. cost-effective production of next-
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etch stop films for damascene Additionally, a wide, central service aisle generation feature sizes using current
interconnect applications. With the significantly eases serviceability by lithography technology. Employing a
Producer’s Twin Chamber architecture, providing 360 degree access to the proprietary plasma-assisted process, the
square4
Issue IV 2009
each wafer undergoes a patented mainframe and chamber backside. system delivers controlled photoresist
in-situ copper oxide removal process Designed for manufacturability, the Lean hole and space CD shrinks of up to 100
prior to BLOk deposition, ensuring Etch has a modular design that nm, creating features as small as 10 nm,
adhesion to copper and superior facilitates production ramp-ups at demonstrating extendibility to the 22
electromigration performance. minimum cost. nm node and beyond. To shrink feature
sizes, the 2300 Motif deposits a thin film
BLOk films enable reductions in the The design allows for both single sided coating on printed photoresist holes and
capacitance of the dielectric film stack (3 chamber) and dual sided spaces. The film is typically the thickness
within the manufacturing process, while configurations (6 chamber), for higher of the desired feature shrink. Using
maintaining etch selectivity availability, and superior productivity. current lithography and mask
and electrical performance, for The system’s compact footprint and technology, the photoresist holes and
continued RC scaling. Proven surface high throughput effectively optimises spaces are printed at a large enough
preparation and initiation layer clean room space and reduces total cost size to optimise exposure latitude and
processes enable BLOk II to be of ownership. The Lean Etch chamber minimize distortion. The shrink process
readily integrated with Black Diamond offers advanced capabilities for is applied after lithographic patterning
and BD II films, ensuring a smooth dielectric etch applications. The to reduce printed features to the
generational transition for 45nm and combination of T-source design with desired size prior to etching. After etch,
beyond devices. instant-on technology and pulsing the film deposited by Motif is removed
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