IC Industry Awards Preview 2009
with enhanced product engineering brightfield and darkfield illumination, a any format feature-profile or film data.
tools and methods tailored for memory substrate handler, and software that
IC products, to more rapidly reduce coordinates the activities. Common models are provided for all
yield loss due to random and systematic scanner tools and user-designed models
defectivity and process-design The Explorer Inspection Cluster is an can be added using the graphic
interactions. edge and backside inspection system interface of the VR Model Editor. These
claiming low cost-of-ownership to the IC features combine to provide a new level
The result is a significant increase in the industry, while the NSX is used for high- of clarity in the precise resolution of
speed at which yield learning can occur volume inspection and metrology of each source of error and yield loss and
during the process ramp, as well as next-generation production processes. its correction path.
enabling higher and more stable yields
during subsequent mass production, the Vector Raptor is claimed to resolve the
The IC Industry Awards
company claims. PDF Solutions’ relative response of multiple feature
will be presented at
designs, design-response to exposure
SEMICON Europa 2009
Integrated Yield Ramp (IYR) and Mass and reticle-scan noise, the lens-slit
Production engagements also include a signature, various contributions of
Issue IV 2009
cross-functional team of engineers that The Explorer’s edge and backside the wafer-process separate from
square4
works on-site collaboratively with the modules both use image-based exposure-tool grid-corrections and the
.com
client to improve client profitability inspection for a more in-depth data set unique contributions of those wafer-
through accelerated yield learning and than light scattering techniques. process-sensitive perturbations of
improved product performance at every enhanced reticle designs (RET) that
stage of IC manufacturing, from early Controlling edge and backside originate in the photomask
ramp through mass production. defectivity has become one of the manufacturing process.
critical factors for enabling 45nm and
PDF Solutions’ offering for the memory 32nm processes, and the Explorer offers Vector Raptor uses TEA Standard Data
oasiasemiconductor
market includes the Back-End-Of-Line a combination of sensitivity and cost of Format workbooks for storage of all
.eur
short-flow CV test chip as well as the ownership to address these issues. In overlay, registration and feature-profile
www
patented Scribe CV, an array of highly- addition, Discover data analysis data as well as analysis reports.
dense test structures that are placed software, offered as an option, further TEA Systems products provide tools
25
directly in the scribe on product wafers enhances efficiency by finding and to import any format metrology data
to provide detailed information on classifying defect pattern signatures, into the standard format workbooks.
variability in the manufacturing line. eliminating the time-consuming task of There is no charge for new-format
classifying thousands of individual updates.
defects.
TEA Systems
Vector Raptor
Rudolph Technologies, Inc
Explorer Inspection Cluster
TEA Systems software product enhances
the control of overlay and registration in
The Explorer Inspection Cluster claims advanced semiconductor manufacturing
fast, accurate and reliable macro to minimise the influence on critical
inspection with flexible configuration of feature dimensions and yield.
multi-surface inspection capabilities. The
Explorer Architecture allows individual Vector Raptor is a seventh generation
systems to be configured with any overlay control tool specifically designed
combination of wafer front, back, and to address the unique problems now
edge module allowing the user to mix being introduced by Double Patterning
and match throughput and inspection and sub-45 nm process-node
type to best fit specific requirements technology.
and reduce cost-of-ownership.
Vector Raptor (VR) provides an object- Winner:Yield Management
The Explorer Architecture is a modular oriented, fully-interactive graphic Best Process 2008
approach to wafer inspection consisting interface for advanced control of Winner FEI Company
of one or more inspection modules with overlay/registration with matching to www.fei.com
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