COVER STORY
19
the METAL_2 pattern. The wafer fabrication flow
time psi RPM directionality material range within
for this phase was as follows;
download removed wafer
(approx) uniformity
1. METAL_1 deposition (0.5µm)
2. METAL_1 lithography
Metal Patterned Wafers:
3. METAL_1 dry etch & resist strip
4. PECVD Oxide ILD deposition (1.5µm) 2:00 4 50/50 Same 3151 1031 4.35%
5. CMP (remove approximately 0.5µm of ILD) 2:00 4 50/50 Same 3718 497 2.20%
6. Clean wafers 3:00 4 50/50 Same 5652 925 4.95%
7. VIA lithography 1:00 4 50/50 Same 1717 466 1.75%
8. VIA dry etch & resist strip 1:30 4 50/50 Same 3088 801 3.36%
9. METAL_2 deposition (1µm) 2:00 4 50/50 Same 4261 321 1.49%
10. METAL_1 lithography 2:00 4 50/50 Same 3872 918 4.12%
11. METAL_2 dry etch & resist strip 2:00 4 50/50 Same 3688 715 3.16%
2:00 4 50/50 Same 3648 1143 5.03%
Conclusion & Future Work 2:00 4 50/50 Same 3580 1169 5.12%
The results were a successful completion of the 2:00 4 50/50 Same 3468 1023 4.44%
development of a CMP planarisation process for 2:00 4 50/50 Same 3655 941 4.15%
the PECVD Oxide inter level dielectric layer in 2:00 4 50/50 Same 3138 804 3.39%
Tyndall’s 1.5µm silicon CMOS device fabrication 2:00 4 50/50 Same 3155 731 3.09%
flow. In addition to developing the CMP process
itself, a post CMP cleaning scheme has been These devices are highly sensitive to surface Table 3: Results of the
developed to return the wafers to the required topography so integrating the CMP process would polish trials. It should
standard of cleanliness to allow for subsequent offer much improved surface planarity and thus be noted that for a
processing. The CMP planarisation process can be better yields. Further work on the optimisation of blanket layer of oxide
extended to other layers in the fabrication flow, for the CMP process itself would be of benefit. The deposited onto an
example to planarise the passivation layer over the most obvious areas to investigate would be the use unpatterned silicon
second metal interconnect layer. This would be of of different slurry solutions & pad types. Further wafer, WiW uniformity
great benefit for complex processes such as work would also be of huge benefit to the post is typically < 2%. For
RF–MEMS devices (these consist of 1.5µm CMOS CMP cleaning process. It is anticipated that patterned wafers,
circuitry with two layers of metal interconnect, further hardware purchase, such as a double sided achieving uniformity
over which micromechanical devices are scrubber system, will be required to support the < 5% after polishing
subsequently fabricated). CMP process in production. would be a very
successful result
Figure 4 and 5: The set of images show both tilted and cross-sectional views of both layers. To
illustrate effectiveness tilted and cross sectional views of wafers are included without the CMP
polish step. The images shown here are taken from a densely packed area of the test chips with
both orthogonal and parallel interconnect lines on the respective METAL_1 and METAL_2 levels.
REFERENCES:
IMEC. “CMP E-Learning Course”.
http://library.nmrc.ucc.ie/elimm/Process%20technology.htm (2004)
A. De Feo. “Material Removal Rate Measurement in Chemical Mechanical Planarization”.
http://me.berkeley.edu/ME107B/cmp/ME107B-defeo.ppt (2006)
Hewlett-Packard. “Chemical Mechanical Polishing (CMP)”. (2005)
Logitech Ltd. “CDP Automatic Equipment Manual, Ref BE-01-79-3” (2005)
Logitech Ltd. “Material Safety Data Sheet, SF1 Polishing Fluid (Syton)”. (2002)
Mid-September 2008
www.euroasiasemiconductor.com
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