COVER STORY
15
Planarisation process for
ILD layers with CMP
A team of researchers from the Tyndall National Institute utilised Logitech equipment
and achieved a CMP planarisation process that leaves a patterned device wafer
smooth and clean enough for further layers of metal deposition. This research will
lead to similar processes where topography is sensitive.
T
he Silicon Fabrication Laboratory at faster polish. Since these come flat, grooves must
the Tyndall National Institute is a be cut into them before mounting on the platen.
silicon CMOS facility running a wide The slurry used for the project is Logitech’s
range of device fabrication process flows. The most standard Oxide CMP slurry, SF1 Polishing Fluid.
complex devices are made on a 1.5µm polysilicon This is a mixture of water, ethylene glycol, and
gate width, two layer metal process flow. Currently amorphous silica. This slurry chemically wears
planarisation is implemented only on the BPSG pre down the wafer, as well as mechanically abrading
metal dielectric (PMD) layer through a high it through friction with the silica particles. For this
temperature reflow step in a furnace. application, the mechanical abrasion far outweighs
In order to enhance the capabilities of the the chemical etching of the slurry.
1.5µm CMOS process it was decided to implement The parameters that can be set on the CMP
CMP planarisation of the PECVD Oxide ILD layer. machine include the slurry flow rate, platen RPM,
This can then be expanded to other layers of the carrier RPM, down force on the wafer carrier,
process flow depending on the applications carrier sweep frequency and amplitude, and the
required (such as planarisation of the passivation revolution direction (counterclockwise or
layer for RF MEMS devices). The enhanced clockwise) of both the platen and carrier. These
planarisation will allow for more aggressive were to be varied to determine the best set of
targeting of linewidths of the interconnect layers as parameters, as well as to see what sort of effect on
well as allowing for the integration of additional removal rate and uniformity each had.
layers of interconnect. Both of these improvements To look at this, wafers had to be investigated
will allow more complex devices to be fabricated. after polishing. Three devices were used for
The aim of this research is to qualify a CMP analysis: an optical microscope, the Nanospec thin Figure 1: The
process for the PECVD Oxide ILD layer in film measurement system, and the scanning diagram below
Tyndall’s 1.5µm CMOS process flow. electron microscope (SEM) illustrate the basic
Wafers were inspected under an optical workings of the CMP
Introduction microscope to look at the residue left by the polish machine
Figure one illustrate the basic workings of the
Logitech CMP machine used for the research. A
soft pad is mounted on a metal platen, which will
have slurry pumped onto it from a tap above. The
wafer is mounted onto a carrier, which is then
pressed down against the pad. The platen and
carrier are spun, rotating either with or against
each other, and as slurry continues to coat the pad
the wafer is polished. A carrier sweep, where the
position of the carrier on the pad is varied, can
also be programmed to run. This also serves to
enhance the uniformity of the polish.
Two different types of pads were used in these
trials. Napcon is a rigid polymer material, which
gives a slower polish rate, and has grooves cut
crisscrossed over its face. These grooves enable the
slurry to run off the pad so it doesn’t puddle at the
centre. The other type of pad, Chemcloth, is softer,
allowing more slurry to be absorbed and provides a
Mid-September 2008
www.euroasiasemiconductor.com
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