18
COVER STORY
around 200Å. large increase in polish rate, but also caused the
During this phase of uniformity to worsen considerably. Tests were done
the project, a number with the platen and carrier set to rotate opposite
of issues associated directions, but this seemed to have little effect on
with the CMP process the outcome of the polish rate or uniformity.
became apparent. The It can be clearly seen from the final image of
slurry tended to build Figure three that the goal of a planarized ILD
up on the pad, layer has been achieved. Some further optimisation
especially at the edges, may be required to more accurately target the final
and this hard crust layer thickness, which is slightly lower than we had
produced an uneven aimed for (1µm). One limitation with the process
polish and low did become apparent during this phase of testing,
uniformity. This made in that the polish uniformity seemed to decline
it necessary to change rapidly after 2 minutes or so of polishing. For this
out the pad, and the application great care needs to be paid to the
frequency of pad polish rate. This could be addressed by using a
Figure 3: The change out was one variable looked at. Also, every more abrasive type of slurry, other than SF1.
progression of time a pad was used for the first time, or for the There was also an investigation into the
polishing over time for first time following a weekend of disuse, it had to generation of defects in the CMP process. Two
the ILD on a patterned be conditioned. Slurry residue also tended to main types of defects occurred, as seen in Figure
metal wafer. remain on the wafers as well, so a method of gently two. The light, puddle shaped mark is from dried
SEM photographs at removing that had to be found. on liquid slurry; the smaller black particles may be
20,000X magnification The issues of slurry buildup and pad wear was from the general environment, from the pad itself
addressed in two ways. One part of the solution or from bits of slurry that dried onto the pad and
meant occasionally conditioning the pad, which let were then picked up by the wafer during polishing.
it revolve on the platen while water ran over it and In production environments this residue is
a metal cylinder swept across and flattened it out. cleaned using a double sided scrubber (DSS),
A twenty minute conditioning run was beneficial which is designed to gently clean wafers after CMP.
for unused pads, as well as after a weekend of This uses brush cleaning with DI water (and
disuse. This provided a small but significant sometimes additional chemical solutions) to remove
increase in polish uniformity. The other half of the both particles and slurry residue.
solution was to replace the pad after five days of With no DSS system available experimentation
use. This offered a very significant increase in with a number of options to clean the wafers
polish uniformity, more than halving the range of sufficiently to allowed further processing of the
layer heights measured on a wafer. wafers without contaminating other process
The second phase of the project switched to equipment. In order to maximise the cleaning
using patterned wafers. The standard METAL_1 effect, a number of these cleaning techniques were
layer of Aluminium/Silicon (1%) was deposited combined together for best result.
then patterned & etched using a standard CMOS Immediately after polishing the wafers were
test pattern. 1.5µm of PECVD Oxide was then dipped in DI water to stop the slurry drying out.
deposited onto the wafers. The same parameter set Then using the other CDP polisher, a short 5
used in the Oxide test wafer trials were used. This second polish using DI water on a clean pad with
resulted in a similar removal rate of, on average, very low down force (1 psi) was carried out.
3607Å. The uniformity range of each wafer, Finally the wafers were given a wet clean in a hot
however, was significantly greater at an average of (85°C) solvent clean solution (DuPont EKC550).
863Å. This was most likely due to the greater This produced a very clean surface on the ILD,
topography variation seen on the patterned wafers. which was good enough to allow the wafers to
It was observed that decreasing the down force continue to the next phase of processing.
Table 2: Results of from 4 psi offered a slower polish with no real The third phase of the project could now
PECVD Nitrate films benefits, while raising it above 4 psi caused the commence, which was to run a short loop
residue and removal wafer’s layer height range to rise significantly. experiment that would encompass all of the process
Increasing the platen and carrier RPM provided a steps involved with the Metal_1 – ILD – METAL_2
interconnect module in the 1.5µm CMOS process
time psi RPM directionality material range within
flow.
download removed wafer
The wafers started as per phase 2, with
(approx) uniformity
patterned/dry etched METAL_1 and ILD
deposition. They were then polished using the same
Nitride Wafers:
recipe parameters as determined in phase 1.
1:00 4 50/50 same 1915 1701 27.57%
Following wafer cleaning as detailed previously (DI
1:00 4 50/50 same 1972 1890 31.21%
soak, short polish with DI, EKC wet clean) the
1:00 4 50/50 same 2359 288 5.45%
polished ILD was patterned & etched to create the
1:00 4 50/50 same 2607 78 1.63%
interconnecting vias between the two layers of
1:00 4 50/50 same 2540 256 5.20%
metal. The second layer of metal was then
deposited, followed by patterning and dry etch of
www.euroasiasemiconductor.com Mid-September 2008
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