16
COVER STORY
process. As the slurry tends to harden quickly, and Oxide ILD wafers. Polishing these blank wafers
the pad can lose tiny pieces of fibre, it was would give us some familiarity with the CMP
essential to see whether the wafers were clean machine, and its rates of polish on the standard
enough to deposit further layers onto the surface. PECVD Oxide ILD layer. This would also give us a
The Nanospec is a spectroscopic reflectometer that chance to vary the settings and observe how
measures the thickness of a thin film. By taking various changes affected the rate and uniformity of
measurements before and after a polish, the rate of polish. Tests were also run on the PECVD Nitride
removal is calculated. The Nanospec also Passivation layer for comparison.
calculates the range of thickness values, which can The next stage was to run polish trials on the
Figure 2: Two main be used to quantify the uniformity of layer across PECVD Oxide ILD layer as deposited over a
types of defects the wafer after polishing. The SEM examines the patterned metal layer (METAL_1). These wafers,
occured in the CMP circuit features under high magnification and in with their more complex topography, were more
process cross section. This showed the topography before accurate representations of what might actually
and after the polish process, as well as at come through the fabrication facility.
Table one: The results intermediate stages. The SEM gave us the clearest The third stage of the project was to run a short
of the polish trials on pictures of the process. loop process integrating the CMP process with two
un-patterned PECVD patterned metal layers and the interconnecting
Oxide wafers. Experimental Methods ‘VIA’ module. The ILD layer is deposited over the
Deposited film To qualify the CMP polish process, a series of three patterned METAL_1 layer and polished smooth.
thickness was 1mm project modules was set out. The first stage was to The VIA pattern is then etched through the now
polish several batches of un-patterned PECVD planarised ILD layer. After the VIA module, the
second metal layer, METAL_2, is then patterned
time psi RPM directionality material range within
and etched.
download removed wafer
(approx) uniformity
Results and Discussions
In the first phase of the project, polishing trials
Test Wafers – Chemcloth:
were carried out on PECVD Oxide test wafers to
2:00 4 50/50 same 3733 Å 256 2.04%
refine an optimal set of polish parameters. Some
2:00 4 50/50 same 3306 Å 311 2.32%
initial process tests had been carried out at
2:00 4 50/50 same 3698 Å 244 1.94%
Logitech’s facility in Scotland during equipment
2:00 4 50/50 same 3886 Å 485 3.97%
source inspection which gave us a starting point.
On the existing 1.5µm CMOS process flow, the
2:00 4 50/50 same 4245 Å 1251 10.87%
PECVD Oxide layer is deposited with a film
2:00 4 50/50 same 4055 Å 947 7.96%
thickness of 1µm. Based on information from a
2:00 4 50/50 same 3809 Å 624 5.04%
number of commercial sources, it was determined
2:00 4 50/50 same 3998 Å 442 3.68%
that for a CMP planarisation process a deposit
2:00 4 50/50 same 4230 Å 627 5.43% approximately 1.5µm of PECVD Oxide be used,
2:00 4 50/50 same 3792 Å 714 5.75%
which will then be polished back to leave 1µm of
2:00 4 50/50 same 3823 Å 511 4.14%
ILD over the METAL_1 structures. Film thickness
2:00 2 50/50 same 1938 Å 493 3.06%
uniformity should be less than 5%.
After testing a number of variables, an optimum
2:00 2 50/50 same 2373 Å 439 2.88%
set of parameters was determined. It was found
2:00 3 50/50 same 2878 Å 552 3.88%
that settings of 4psi down load, with carrier and
2:00 3 50/50 same 3076 Å 215 1.55%
plate both at 50 RPM and rotating in the same
2:00 3 50/50 same 2713 Å 219 1.50%
direction, and a carrier sweep and frequency of
2:00 5 50/50 same 4373 Å 391 3.47% 10% of maximum, running for two minutes, would
2:00 5 50/50 same 4609 Å 395 3.66%
achieve the results. The uniformity was within
3:00 4 50/50 same 5885 Å 1113 13.52%
limits, at an average thickness range of 468Å.
2:00 2 50/50 opposing 2397 Å 435 2.86%
The Chemcloth pad was used in most of these
2:00 4 50/50 opposing 3998 Å 981 8.17%
tests, and a slurry flow rate of 100ml/min was
found to be sufficient. We also experimented with
2:00 4 75/75 same 5971 Å 1164 14.45%
using the Napcon pad providing a much slower ILD
2:00 4 100/100 same 8110 Å 1070 28.31%
removal rate that was inadequate. Table one
2:00 6 50/50 same 5678 Å 861 9.96%
illustrates the results of the tests.
1:00 4 100/100 same 3660 Å 809 6.38% Trials were also ran on wafers with PECVD
2:00 4 25/25 same 1837 Å 461 2.82% Nitride films. It was found that the same settings
Test Wafers – Napcon
of 4psi down load, with carrier and plate at 50
2:00 2 50/50 same 749 Å 251 1.36%
RPM and rotating the same direction, and a
2:00 4 50/50 same 1030 Å 453 2.53%
carrier sweep and frequency of 10% (of maximum
deflection), running for one minute, would give us
2:00 4 50/50 same 1090 Å 520 2.92%
an average removal of 2279Å. With a clean pad,
1:00 4 50/50 same 562 Å 225 1.19%
these wafers came out with an uniformity of
www.euroasiasemiconductor.com Mid-September 2008
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