Molded underfill process for the SiP
!
!"#$ !%#$
Figure 6. FM (foreign material) contamination
images. (a) Leg 5 image. (b) Leg 6 image.
!
Figure 8. Window warpage graphs with Legs.
process conditions. Base resin Mar 4/ LV,
Figure 7. Internal void and de-lamination images. Failure happens only for Leg 8.
maximum filler dimension 20 µm, Spiral
flow 160 cm @ 175˚C, and filler content
88% EMC is best material in terms of
performance.
Resin flow speed during transfer is
the main cause of void formation. So, it is
affected by process parameters, resin pass
dimensions and shape. Short transfer time
and low pressure cause resin velocity fluc-
tuation, and ultimately it traps voids. Ac-
cordingly, a long transfer time and enough
pressure to overcome register pressure are
needed to get rid of trapped voids. In this
test, 1000~1200 psi transfer pressure and
over 10 seconds of transfer time show good
results.
The MUF process shows reliable
results and good reliability test results. In
the near future, this process will be used
for small dimension multi flip-chip SiP.
Nevertheless, additional tests to determine
chip dimension and material property ef-
fects are needed to integrate MUF process
Figure 9. Second test sample SAT images. (a) Leg 1, (b) Leg 2, (c) Leg 3, (d) Leg 4, (e) Leg 5 as main encapsulation methods of SiP
production.
design. This is why all those properties tion or void. Figure 11 is a cross-sectional
affect resin flow speed and shape.
acknowledgements
image of MSL 2 tested MUF sample.
JEDEC Level 3 & 2 260˚C tests are
The authors would like to thank the Sam-
This sample is polished from the bot-
done to compare the reliability level of the
sung-Electro Mechanics for this research
tom side of PCB, and analysis is done with
MUF sample with capillary underfilling
work and all project members.
an optical microscope from top to chip
and molding sample. bottom. No voids or delaminations are de-
references
Figure 10 is capillary underfill sample tected. Bumping ball shape is spherical. No
1. Tong Yan Tee, Chek Lim Kho, Daniel
images. Figure 10(a) is an optical micro- micro voids are detected near the bumps.
Yap, Carol Toh, Xavier Baraton, Zhao-
scope image after underfilling. 10(b) is Test results mean that the MUF process
wei Zhong, Micoroelectronics Reliabil-
a SAT (image after molding. Capillary for sample multichip SiP is no problem.
ity, V.43, 2003, pp.741.
underfilling is considered to be the best So, additional reliability tests are needed to
2. Shin-Ping Liu, Chun-Tai Wang, Chun
process for the flip-chip underfilling. determine long-term reliability.
Hsien Lee, Wei Wang, “Miniaturzed
However, it has its disadvantages, such as
WiFi System module using SiP/IPD
dispensing spacer, higher moisture absorp- conclusion
for handheld device applications,”
tion and long process time. So, it is caused In this experimental test, the MUF
Proceeding of IMPACT 2007 Interna-
by bottleneck from SiP process. In this (molded underfill) process for SiP (system
tional, October 2007. pp.146
test, both process samples have passed the in package) has been developed. EMC ma-
3. Matti Mantysalo and Eero O. Risto
MSL3 and 2 tests without any delamina- terial is found and optimized to the right
www.globalsmt.net Global SMT & Packaging – December 2008 – 15
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