Molded underfill process for the SiP
Molded underfill process
for the SiP
by Tae Hyun Kim, Ki Chan Kim, Sung Yi, Dong-Kuk Kim, Tae Sung Jung, Jin Su Kim, and Joseph Y. Lee,
Samsung Electro-Mechanics Co., Ltd., Gyunggi-Do, Korea
introduction
Nevertheless, additional dispensing space is
There is an increasing trend toward
For our application and
needed, and low throughput is a problem.
miniaturization in the electronics industry.
As the density of package areas to substrate
experiment, a new underfill-
Electronic products are getting smaller,
increases, the throughput advantage of
ing process, molded underfill
lighter, and faster
1
. This is why there is a
transfer molding rises exponentially
5
. For
(MUF), is being investi- demand for more compact and efficient elec-
flip chip packages, there are underfilling
gated. A few companies have tronic packaging. For example, convergence
and, subsequently, overmolding processes.
already tried to develop this
is a main trend in the mobile phone sector.
The single step transfer molding of both
process using one flip chip.
Communication is the basic function in the
layers results in substantial cost savings and
In this application, we are
cell phone, but personal computers, camer-
removes the dispensing step
6
. These factors
molding three flip chips into
as, camcorders, games, movies, broadcasting
drive much investigation in newly developed
the underfill process. The
media, and navigation functions are being
molded compounds that offer underfill and
added, with additional features like WLAN
2
.
test vehicle consists of three
overmold packages in a single step.
So, chip integration technology is needed.
3.5 x 3.5 mm flip chips, one
So, MUF process feasibility with mul-
SiP (system in package) can offer many solu-
tichip SiP is being studied here. The test
saw filter and several passive
tions to package level system integration
3
.
vehicle is 11 x 11 mm and is 3.5 mm thick
components. The package
On the other hand, to achieve reliable
with three flip chips, two band pass filters
dimensions are 11 x 11 mm, SiP requires many process improvements
and 22 passives. Two classes of bumped
and the substrate has four and developments. The use of flip-chip
chips are being compared in terms of the
layers with a thickness of 0.3
interconnection has inherent advantage over
underfilling effect, with different bump
mm. Two classes of daisy chin
the conventional wire bonding techniques
structure, one a 144 each full array bump
chips are used as dummies to
for electronic packaging in terms of higher
structure and the other a 65 each random
perform DC electrical tests.
packaging density with better performance.
array bump structure chip. The substrate
Vital process factors are
In flip-chip packaging, underfill is com-
consists of four layers for the BGA type,
monly used to reduce a thermo-mechanical
determined, then the process
while the solder register is AUS320.
deformation caused by the thermal expan-
conditions are optimized.
In this test, eight classes of EMCs are
sion mismatch between the silicon chip
evaluated and the best EMCs is chosen from
Afterwards, a comparison is
and organic substrate, as well as solder joint
among them. The critical points are internal
made between the reliability
reliability improvements
4
. Process for the
void, external void, and warpage. From this
level of a MUF sample and a majority of flip chip packages includes a liq-
test, EMCs and the MUF processes are to be
conventional underfilled and uid underfill gap between the substrate and
determined.
molded sample. Tthe reliabil-
chip and a secondary process where the chip
ity test of the MUF sample
itself is protected from mechanical damage.
experiment
shows good promise.
The liquid underfilling is highly flexible and
Test vehicle
reliable, with a small void-forming process.
Figure 1 shows the test vehicle: (a) is cross-
section structure; (b) and (c) are top and
!
bottom views. The unit is 11 x 11 mm and
Keywords: SiP, Underfilling,
1.2 mm in height. It contains a 0.8 mm
Encapsulation, MUF (Molded
!
Underfill)
Figure 1. Test vehicle structure: (a) cross-section, (b) top Figure 2. Daisy chain design (a) DC1 bump structure
This paper was originally presented
view, and (C) bottom view. (b) DC 2 & 3 bump structure.
at SMTAI 2008.
12 – Global SMT & Packaging – December 2008
www.globalsmt.net
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