Molded underfill process for the SiP
mold cavity height with 0.4 mm thick SMTs are placed with filter and passives Finally, a reproducibility test confirms the
substrate. From the top view, three chips while flip chips are positioned by flip result. SAT (scanning acoustic transmitter)
can be seen. DC1 chip has 144 bumps as chip bonder. During the flip chip bond- T-scan and C-scan are used for internal
full array. DC2 has 65 bumps as random ing process, die tilting and rotation are void and underfill void. For the final con-
array. Figure 2 shows DC1 and DC2 bump reduced. For the soldering, lead-free reflow firmation, cross-section analysis is done.
structure. The bump diameter has 100 condition is used. In the molding process,
µm height, 140 µm diameter and 250 µm a vacuum chamber molding machine is Material selection
pitch. All chips’ dimensions are 3 x 3 mm. used to increase the mold flow ability and The selection of resin and filler package
Substrate dimension is the convention- to reduce trap void. Applied vacuum is at is critical to achieving good encapsulation
al 230 x 62 mm. It contains four window 30 Torr. Critical parameters like X-Y matrix characteristics. A general rule of thumb
blocks while each block contains a 4 by 4 and one-way ANOVE analysis are applied. is that the filler particle dimension must
unit. One strip has 64 units. Three critical factors—EMC material, be no more than one-third the minimum
transfer speed, and transfer pressure—are gap the compound must fill
7
. So, the
Process summary chosen from 14 potential factors, and critical point of material selection is filler
In this test, conventional packaging process three tests are done. In the first test, two of dimension and spiral flow. Eight materials
is used. Wafer sawing, filter and passive the best EMC materials are selected from are selected. Those materials come from
SMT, flip chip, reflow, flux cleaning, eight. In the second, a design of experi- four different vendors. Each has different
plasma cleaning and molding are inte- ment (DOE) test determines transfer speed physical and chemical properties. Table 3
grated for our application in one package. and transfer pressure to be critical factors. shows the material property briefly. The
max filler dimension is 45 µm with mini-
mum dimension of 20 µm. Chip stand off
Table 1. First test Legs. The other conditions, such as transfer time and speed are set as standard conditions.
height minimum of 50 µm after reflow is
expected. So, a max filler dimension below
Leg EMC Transfer pressure Transfer time
45 µm is selected.
1 Sample 1 1200 psi 15 sec
Spiral flow has wide range. The mini-
mum flow length from sample 3 is 130
2 Sample 2 1200 psi 15 sec
cm while its maximum is at 180.3 cm with
3 Sample 3 1200 psi 15 sec process temperature of 175˚C.
4 Sample 4 1200 psi 15 sec
results and discussion
5 Sample 5 1200 psi 15 sec
At the first stage test, 1200 psi transfer
6 Sample 6 1200 psi 15 sec
pressure at 15 seconds transfer time is
used. It is set at normal condition. After
7 Sample 7 1200 psi 15 sec
molding, PMC (post mold cure) at 175˚C
8 Sample 8 1200 psi 15 sec
is done for six hours. During the mold-
ing process, 28 ton clamp force is used
to reduce flash. However, there is a little
Table 2. Second test Legs DOE table. Two EMCs are selected. First tests: transfer time & speed DOE factors.
bit of lash because the filler dimension is
Leg EMC Transfer Transfer Leg EMC Transfer Transfer
quite small. To remove this flash requires a
pressure time pressure time
change of mold chase design.
So, in this test, flash problems are
1 Sample 1 1200 psi 15 sec 5 Sample 5 1200 psi 15 sec
ignored. At the first test, five items of
2 Sample 2 1200 psi 15 sec 6 Sample 6 1200 psi 15 sec
MUF void (under flip chip), internal void,
external void, window warpage and other
3 Sample 3 1200 psi 15 sec 7 Sample 7 1200 psi 15 sec
external visual defects are tested. Figure 3
4 Sample 4 1200 psi 15 sec 8 Sample 8 1200 psi 15 sec shows good sample images. This image
is scanned from SAT (scanning acoustic
transmitter) analysis and shows no voids
Table 3. EMC material property.
under chips.
EMC Base resin Max filler size Spiral flow Filler content
From the image, the solder bumps can
(@175˚C/cm) (wt%)
be seen. Nevertheless, all three chips show
no void. The right side image is a C-scan
Sample 1 Biphenyl 20 µm 150 87
image while the left side image is T-scan
Sample 2 Biphenyl 30 µm 150 88
image. However, the void-formed sample,
Figure 4, shows big voids under each chip.
Sample 3 Crystalline 30 µm 130 86
At the C-scan, the void shows white and
Sample 4 Mar 4/LV 20 µm 160 88 bright image, but at the T-scan, the void
shows as a black spot. The black spot on
Sample 5 Mar/LV 45 + 25 µm 165.1 87.5
the left top side at the T-scan image is a
Sample 6 Mar/HCDR 45 + 25 µm 180.3 87.5
filter. The filter has spacer. Even though
Sample 7 Mar/HCDR 45 180 87
it shows as black spot, it is not a void. The
underfill void is large. It seems to cause
Sample 8 Biphenyl 45 139.7 88.5
significant damage to the package reliabil
www.globalsmt.net Global SMT & Packaging – December 2008 – 13
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