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MICRONANOSYSTEMS
packages e.g. SSOP, QFN, QFP including Amcor, ASE,
Boschman, Carsem and UTAC. In addition, a number of
companies specialising in MEMS packaging exist including
Aspen Technologies, ePack, and Microassembly Technologies. As
we noted earlier, a thoroughly adequate infrastructure exists to
support the packaging of MEMS-based systems solutions from
prototyping to large scale production.
Having said this, what are the innovative and unique
technologies that are being developed to overcome this
packaging challenge? I believe some of the more significant are
ec
3-D die stacking, through hole vias (THV) and wafer level
packaging (WLP).
3-D die stacking is becoming quite popular both in the IC and
MEMS area. The use of this approach minimises used area on
the substrate/board on which the MEMS die is mounted.
However, once the MEMS chips and its signal conditioning chip
are stacked, one has to provide connections for these devices.
Some use the technique of external bond wires as is illustrated
in Fig 4 which shows Aspen Technologies approach to mounting
Image courtsey of SUSS MicroT
an optical MEMS chip to a CMOS controller chip.
Figure 5: In-situ adhesive wafer bonding of glass wafers More recently, through hole vias are becoming the technology
with micro lenses. The bond is performed in a mask of choice. It is interesting to note that in the research to write
aligner with the adhesive being cured by ultra violet this article, we uncovered that “ THV’s were used in the SCAP
radiation (Silicon Capacitive Absolute Pressure) sensor designed and
manufactured by Ford in the early 80’s using a laser to create
the holes in the glass that were subsequently metalised and that
environmental requirements including vacuum and hermeticity. capped the sensor” stated Joe Giachino, Former Ford sensor
Finally it enables precision placement and alignment relative to designer and currently External Programmes Director of the
other devices and connections in the system” she added. University of Michigan WIMS. Here is a situation where
WIMS Najafi in his seminal 2003 paper, “Micropackaging MEMS technology has been adopted by the IC industry.
Technologies for Integrated Microsystems: Application to Chip Spangler, VP and CTO at Aspen Technologies said, “The
MEMS and MOEMS”
[3]
stated that “there are several key synergy between thin electronics, wafer level packaging and
technological challenges to the packaging of MEMS and they through-hole vias allowing die stacking to become mainstream is
can be categorised under three general topics: 1. MEMS device now underway and has been driven by MEMS adoption into
encapsulation(protection), connection and assembly (Fig 3). portable electronics. This technology has its root in MEMS”.
There are many reasons for this chief amongst these being that Note: Spangler did early work on the Ford SCAP while a
most MEMS devices work in a multi-domained fashion i.e. graduate student at UMICH. Through hole vias are typically
electro-mechanical, electro-chemical, electro-optical whereas IC vertical but startup ePack is providing both traditional vertical
devices typically work in a pure electronic domaine. as well as lateral vias. The lateral polysilicon feed through
MEMS packages not only need to withstand shock, vibration, approach can be used in CMOS and used a low temperature
moisture but to work properly, they must be immersed in the (200 degrees C) LPCVD process. This approach is presently
environment that they need to measure e.g. a blood pressure
sensor or an oil pressure sensor. These media are chemically
harsh and the MEMS device must be physically isolated from
the media while still maintaining the ability to be in contact
with it…and this is not a paradox!
“MEMS packaging must be designed to encapsulate and
protect the MEMS (and other system components) while engage
the device with the media that it must measure” stated Eric
Leonard, a packaging consultant who chaired a packaging panel
at the MIG METRIC conference. ‘In addition, the package must
be designed NOT to interact with the MEMS device and impart
stresses to it which will affect its performance especially over
large temperature ranges. The package thus must be rugged and
be designed in a cost-effective fashion.’
There are a number of commercial packaging house available
to support MEMS device developers. On one side we have the Fig 6: The five layer microfluidic device is used for DNA
classical semiconductor packaging houses who tend to want to amplification and has layers of etched Silicon and patterned
Image courtsey of Infotonics
work with companies that can use standard semiconductor polymer layers joined together using a submicron thick adhesive
www.micronanosystems.info December 2008 / January 2009
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