EVG Cover Story v Final_DR 18/12/08 10:48 Page 15
COVER STORY
15
The name’s Bonding,
Wafer Bonding
As an enabling technology for new applications, wafer bonding becomes increasingly
invaluable for future wafer applications and products. Paul Lindner, Executive Technology
Director and CTO of EV Group explains the challenges and necessities for this technology.
A
s the nanoscale era progresses, innovative A brief history
processes are implemented with an eye toward Wafer bonding was first developed for the MEMS market,
keeping on the path of Moore’s Law. Wafer primarily as a wafer level capping technique. The manufacturer
bonding, joining two wafers or substrates using a suitable would produce a MEMS wafer with some fragile structures, and
combination of process technologies, chemicals and adhesives, is would then use another wafer to cap off and protect the MEMS
one such innovation. Originally developed as a back end process structures, sealing off the cavities around them to prevent
for manufacturing fragile MEMS devices and structures, wafer contamination. Today, instead of capping, wafer bonding is being
bonding has proved invaluable for silicon on insulator (SOI) and used for 3D interconnect to stack different wafers. Industry can
other engineered substrates. Consequently, wafer bonding is take a MEMS wafer, a memory wafer and a CMOS logic wafer,
moving further into front end manufacturing. stack them on each other, and then connect them by using TSVs.
Additionally, advanced packaging techniques are gaining The companies implementing these 3D integration bonding
momentum. According to the international technology roadmap schemes are working in front end manufacturing environments.
for semiconductors (ITRS), as traditional CMOS scaling nears They are emerging from the CMOS rather than the MEMS
its natural limits, other technologies are needed to enable world. Integrating wafer bonding into front end manufacturing
continued progress. Key approaches that have outpaced ITRS requires the bonder to accommodate such front end
forecasts include wafer level packaging (WLP) and 3D manufacturing requirements critical to CMOS structures, such as
integration, which can accommodate the size, power, enhanced cleanliness and absence of lead. This significantly
performance and functionality demands dictated by consumer impacts the front end, as MEMS’ role in consumer applications
electronics, and enabled by wafer bonding technology. grows more ubiquitous. Already in wide use in automotive and
As a provider of wafer processing solutions for semiconductor, other applications, MEMS based sensors such as gyroscopes and
MEMS and nanotechnology applications, EV Group (EVG) holds accelerometers will soon be able to improve the interactivity and
a significant share of the market for wafer bonders. The sensitivity of the cell phones and other mobile devices into which
company has built this position by leveraging core strengths and they’re integrated.
with its ongoing R&D, which has opened up new opportunities
for the company to make inroads to high volume manufacturing
(HVM) market. As EVG customers, particularly those in MEMS
markets, increasingly demanded solutions that could be used for
both temporary and permanent bonding applications, the
company pioneered development of integrated systems
specifically designed to be able to handle both types of bonding,
depending on the customer’s needs. This effort has driven a
significant shift in EVG’s installed base; today, 70-80% of EVG
wafer bonders are sold into HVM environments, and its flagship
GEMINI bonder has double digit growth for four years.
Moreover, through its close partnerships with other industry
leading suppliers, EVG is manoeuvring its market position into a
leading role promoting the broad adoption of through silicon vias
(TSVs), a key technology for both wafer level packaging and 3D
integration, and looking beyond Moore’s Law to new system in Figure 1. Optically aligned wafer bonding with separated
package (SiP) applications. process modules for alignment and bonding steps
December 2008 / January 2009 www.euroasiasemiconductor.com
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