EVG Cover Story v Final_DR 18/12/08 10:48 Page 16
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COVER STORY
When an adhesive serves as the bonding agent, photoresist,
spin-on glass or polymers are used to deposit a planarising
material between two wafers, enabling low temperature
annealing. This process is particularly well suited for creation
of low stress wafer stacks
Also emerging is a wafer bonding application that combines taking advantage of the conductive properties of the glass, the
various materials to enable design and manufacture of novel anodic process creates covalent bonds and a hermetic seal.
devices. These engineered substrates include unique combinations First used for precision aligned bonding and now being
of materials, such as gallium arsenide (GaAs) on silicon and employed for permanent bonds in CMOS image sensor (CIS) and
germanium (Ge) on silicon, used in optoelectronics. Typically, 3D package stacking, thermo compression bonding employs
these materials are quite fragile, and temporary wafer mechanical pressure to wafer bonding substrate materials using
bonding/debonding techniques are ideally suited for handling thin intermediate layers and materials such as glass frit or gold to
wafers, which yield chips for advanced applications such as encapsulate sensor cavities (see Figure 2). Bonding takes place
smart cards and small, handheld mobile/wireless electronics. at temperatures up to 550
o
C combined with mechanical
Ensuring a successful bond is also dependent upon the pressures up to 60 kiloNewtons (kN). Separation between the
bonding systems’ ability to maintain alignment accuracy between bond pads using a bond chuck enables uniform encapsulation of
the two wafers being bonded, as alignment quality can vary, any gas or vacuum in etched cavities.
depending on product and process requirements. For example, Eutectic bonding is a metallic bonding approach often used
3D stacking applications, which help improve device packing for MEMS sensors, which require a hermetic or vacuum seal. An
density and signal delays without negatively impacting yield, are intermediate bonding material is used at a specific temperature
particularly dependent on precise alignment of the wafers. Any to form a eutectic alloy, such as gold silicon (Au-Si), gold tin
variation can greatly affect electrical performance of the devices. (Au-Sn), or lead silicon (Pb-Si). The metals are usually deposited
Figure 1 illustrates the underlying technology principle employed by plating, while the silicon can be the wafer or CVD.
in EV Group’s alignment systems. For wafer bonding to be Solid/liquid mixing occurs at temperatures slightly above the
successful, the two surfaces being bonded must be clean, flat and eutectic point and high contact force (40 kN). A hermetic solid
mirror polished, with key process variables, such as temperature seal forms upon cooling. When an adhesive serves as the bonding
and force, controlled and applied as appropriate. Bonding can be agent, photoresist, spin-on glass or polymers are used to deposit
either permanent or temporary. a planarising material between two wafers, enabling low
temperature annealing. This process is particularly well suited
Permanent bonding for creation of low stress wafer stacks.
The most common types of permanent bonding are anodic, Silicon direct bonding, also known as fusion bonding, is
thermo compression and silicon direct, while eutectic and becoming an increasingly important process as methods to
adhesive bonding employ a ‘bonding agent’ in the interface, reduce annealing temperature are developed. Wafers can be
composed of metal and metallic alloys or organic adhesives. aligned and brought into contact under ambient conditions in the
Anodic bonding is a surface reaction based bond commonly aligner, with special loading chucks used to prevent
used in wafer level packaging (WLP). The process unites a contamination of bonded surfaces. After alignment, the wafers
silicon wafer with a glass wafer, typically Pyrex, which features a are brought into contact starting from the centre and working
high concentration of alkali metal oxides. At high temperatures towards the edge. This guarantees excellent, void free bonding
(up to 550
o
C), a high voltage (up to 2000V) electric field is results. Pre-bonding under vacuum and the subsequent pre-
applied. This dissociates the oxides, driving the metal ions into annealing can be performed using a bond tool similar to that
the glass and resulting in an oxygen rich layer at the interface used in anodic or pressure bonding, but with Teflon coated
between the two wafers. The electric field forces the oxygen ions surfaces. This approach can be used for SOI bonding, as well.
to the silicon surface, resulting in a strong, irreversible bond. By
Temporary bonding/de-bonding
As mentioned previously, temporary bonding is needed for ultra
thin devices used in smart cards and other portable applications.
In some cases, these thin substrates can be less than 100 µm
thick, so they are very fragile, and yield can be compromised if
they are not handled appropriately. Sapphire carriers are most
commonly used because they can be machined to a very high
Figure 2. Intermediate layers deposited on one or both thickness tolerance.
wafers act as bonding adhesive A typical process flow for temporary bonding (see Figure 3)
www.euroasiasemiconductor.com December 2008 / January 2009
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