Manufacturing
Right: Fig. 9 Scaling of
the printed and the
physical gate length
according to the 2008
ITRS update. Source:
2008 ITRS Summer
Public Conf.
Far Right: Fig. 10
Statistical variability
reduction scenario.
Source: 2007 ITRS
Winter Public Conf.
behind the introduction of metal gate will be great difficulties in achieving reasonable
technology, fully depleted SOI and FinFET statistical variability in bulk MOSFETs at the
devices is the promise of a reduction in statistical 22nm technology generation. The introduction
variability. However this analysis is based on the of high-k/metal gate has its own problems from
assumption that the main source of statistical the variability point of view. Although it reduces
variability are the random discrete dopants. The the EOT it introduces new variability sources
results of the numerical simulations presented in compared to the old fashioned SiO
2
gate stack
this paper clearly illustrate that due to technology. First of all the high-k dielectric has
uncertainties in the future technology solutions lower quality and higher density of fixed/trapped
and capabilities Figure 10 represents at this charges. As illustrated in Figure 7 and Table 2
moment of time only wishful thinking. As Fig. 6 this can significantly increase the variability in
illustrates, if LER remains at its current level of 4- fully depleted SOI MOSFETs. Furthermore, the
34
5nm at 20nm physical channel length it will p-channel high-k transistor is more susceptible to
become the main source of statistical variability negative bias-temperature instability (NBTI)
www
in bulk MOSFETs. LER is mainly determined by which can cause increase of the statistical
.eur the physics and the chemistry of the 193nm variability with aging. This situation is
oasiasemiconductor
photolithography process which has been exacerbated by the creeping positive bias-
struggling to deliver the required reduction in temperature instability (PBTI) n-channel high-k
the feature size for few technology generations. transistor which was insignificant in their SiO2
The lack of a clear successor to 193nm gate stack counterparts. The granularity of the
lithography questions the lithography’s capability high-k dielectric and the metal gate have also
to deliver the much needed reduction in LER. become a concern from the statistical variability
.com
The introduction of a high-k/metal gate stack by point of view.
Intel at the 45nm technology generation indeed
reduced the statistical variability due to a Conclusions
square4
Issue II 2009
pronounced reduction of the equivalent oxide The statistical variability introduced by
thickness (EOT). The question is to what extent discreteness of charge and matter has become
the technology will be able to reduce the EOT one of the major concerns for the industry.
below the current 1nm mark. Figure 7, which is Increasingly, the strategic technology decisions
benchmarked against the measured variability in that the industry will be making in the future will
the Intel 45nm technology, indicates that if the be motivated by the desire to reduce statistical
planned ITRS EOT reduction is achieved, the variability. The useful life of bulk MOSFETs, from
useful life of the bulk MOSFET from the the statistical variability point of view, can be
Table 2: Summary of statistical variability point of view may be extended below the 20nm technology mark only
simulation results with extended below a 20nm channel length. if the LER and the EOT could be successfully
trapped charges However if EOT cannot be scaled further there scaled to the required values. The introduction
of fully depleted SOI MOSFETs and perhaps
FinFETs will be mainly motivated by the
necessity to reduce the statistical variability. This
however might be jeopardised by other sources
of variability associated with the introduction of
high-k/metal gate stacks and increased statistical
reliability problems.
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