Manufacturing
Variability in CMOS scaling
Asen Asenov of the Device Modelling Group Department of Electronics and
Electrical Eng. at the University of Glasgow analyses the ITRS roadmap in light of
recent simulation results of 45nm technology using his departments ‘atomistic’
device simulator, which at present is the most sophisticated tool for predictive
simulation of statistical variability introduced by discreteness of charge and matter.
Issue II 2009
square4
.com
V
ariability of transistor Methodology and Validation
characteristics has become a The University of Glasgow’s statistical 3D device
major concern associated simulator solves the carrier transport equations
with CMOS transistors in the drift-diffusion approximation with Density
oasiasemiconductor
scaling and integration. It Gradient (DG) quantum corrections. The major
.eur
already critically affects SRAM scaling and sources of statistical variability are automatically
www
introduces leakage and timing issues in digital included in the simulations. Until recently, for
logic circuits. It is the main factor restricting the conventional bulk MOSFETs (still the workhorse
29
scaling of supply voltage, which for the last four of CMOS technology) Random Discrete Dopants
technology generations has remained virtually (RDD) illustrated in Fig.1, Line Edge Roughness
constant, adding to the looming power crisis. (LER) illustrated in Fig. 2 and Poly Gate
Statistical variability has become a Granularity (PGG) illustrated in Fig. 3, were the
dominant source of variability for the 45nm most important sources of statistical variability.
technology generation and cannot be reduced With the introduction of high-k/metal gate stacks
by tightening process control. While in the case the granularity of the gate dielectric and the
of systematic variability the impact of metal gate also start to play an important role.
lithography and stress on the characteristics of In the simulations, the RDD are generated from
an individual transistor can be modelled or a continuous doping profile achieved by placing
characterised and therefore factored into the dopant atoms on silicon lattice sites within the
design process, in the case of statistical device source/drain and channel regions with a
variability only the statistical behaviour of the probability determined by the local ratio
transistors can be simulated or characterised. between dopant and silicon atom concentration.
Two adjacent macroscopically identical Since the basis of the silicon lattice is 0.543nm a
transistors can have characteristics from the two
distant ends of the statistical distribution. How
is it reflected in the 2008 update of the ITRS?
We review the major sources of statistical
variability in nano CMOS transistors focusing at
the 45nm technology generation and beyond.
The dominant sources of statistical variability
including random discrete dopants, like edge
roughness and poly silicon granularity will be Above: Fig. 1(a): KMC
discussed in detail. This is followed by simulation simulation of RDD (11)
results that illustrate the trends in statistical
variability with scaling in bulk, thin body SOI Left: Fig. 1(b):
MOSFET architectures. Finally we elaborate on Potential distribution
the impact that statistical variability has on the in a 35 nm MOSFET
current edition of the ITRS. subject to RDD
Page 1  |  Page 2  |  Page 3  |  Page 4  |  Page 5  |  Page 6  |  Page 7  |  Page 8  |  Page 9  |  Page 10  |  Page 11  |  Page 12  |  Page 13  |  Page 14  |  Page 15  |  Page 16  |  Page 17  |  Page 18  |  Page 19  |  Page 20  |  Page 21  |  Page 22  |  Page 23  |  Page 24  |  Page 25  |  Page 26  |  Page 27  |  Page 28  |  Page 29  |  Page 30  |  Page 31  |  Page 32  |  Page 33  |  Page 34  |  Page 35  |  Page 36  |  Page 37  |  Page 38  |  Page 39  |  Page 40  |  Page 41  |  Page 42  |  Page 43  |  Page 44