Manufacturing
Fig. 7: Channel length
dependence on
standard deviation of
the threshold voltage
introduced by random
dopants, line edge
roughness and poly-Si
granularity: (A) tox
scales according to
ITRS; (B) oxide
thickness= 1nm
Issue II 2009
square4
Fig. 6: Channel length dependence on standard
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deviation of the threshold voltage introduced by
random dopants, line edge roughness and poly-
Si granularity: (A) LER scales according to ITRS;
(B) LER = 4nm
results of the impact of RDD, LER and
oasiasemiconductor
fixed/trapped charge with different aerial density
.eur
on threshold voltage variation are summarised in
www
Table 2 on the follwing page. Fig. 8: (1) Typical potential profiles corresponding to trap charge with sheet
density at (a) 1e11cm-2, (b) 5e11cm-2, and (c) 1e12cm-2
33
Impact of the variability
on the ITRS
The 2008 ‘update’ of the ITRS has introduced
Europe’s international conference
profound changes to the definition of
technology generations and the corresponding
on CMOS variability
physical gate length of transistors compared to
the 2007 ‘full edition’. Some of these changes
have been motivated to a great extent by The National Microelectronics Institute (NMI), the trade association
concerns about statistical variability. The representing the semiconductor industry in the UK and Ireland, in
dramatic disparity between the number in nm collaboration with the UK’s nanoCMOS Consortium, is to host its second
identifying the technology generation (which international conference on CMOS variability, 12-13th May 2009 at the
itself is now divorced from the definition of the IET’s Savoy Place, London.
half pitch and has become purely a commercial
pointer) and the physical gate length, present in Aimed at chip designers, technology developers, wafer foundries
the 2007 ITRS edition, practically disappears at and EDA tool vendors, ICCV 2009: “Living with Variability” will explore
the 22nm technology generation in the 2008 the real impact of CMOS variability and how it can be managed at
ITRS update. 45nm and below. Sessions presented by world leading experts will
Figure 9 illustrates this trend. Bearing in introduce the issues, discuss the options and share techniques for
mind that the 2008 ITRS update extends the life meeting the challenges of CMOS variability head-on. This will provide a
of bulk MOSFETS to 2016 and looking into the strong foundation to begin discussions for future needs in what will
variability explosion below 25nm physical become an increasing challenge for the industry.
channel length in Figs. 6 and 7 it becomes
immediately obvious what is one of the main Recognised experts confirmed to speak at what is Europe’s only
motivations for such a drastic return to realistic dedicated conference on CMOS variability include:
physical channel lengths. Dr Kelin Kuhn, Intel Fellow, Technology and Manufacturing Group
In the past the research into new gate stack Dr Sani Nassif, IBM Austin Research Laboratory
materials and new device architectures has been Jean-Marie Brunet, Mentor Graphics
mainly motivated by the drive to improve the Krisztián Flautner, ARM
device performance. Not any more. As Professor Asen Asenov, nanoCMOS Consortium (Uni of Glasgow)
illustrated in Fig. 10 the main driving force
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