Manufacturing
The validation of our simulation technology is
done in comparison with measured statistical
variability data in 45nm LP CMOS transistors.
The simulator was adjusted to match accurately
the carefully calibrated TCAD device simulation
results of devices without variability by adjusting
the effective mass parameters involved in
Above: Fig. 2(a): density gradient approach and the mobility
Typical LER in model parameters. The calibration results are
photoresist (Sandia shown in Fig. 4, where ‘low’ and ‘high’ drain bias
Laboratories) are 50mV and 1.1V respectively.
The simulation results for the standard
Right: Fig. 2(b): deviation of the threshold voltage introduced by
Potential distribution individual and combined sources of statistical
in a 35 nm MOSFET variability are compared with the measured data
subject to LER in Table 1. In the n-channel MOSFET case the
accurate reproduction of the experimental
measurements necessitates the assumption that,
fine mesh of 0.5nm is used to ensure a high in addition to RDD and LER, the PSG related
resolution of dopant atoms. However, without
considering quantum mechanical confinement in
the potential well, in classic simulation, such a
fine mesh leads to carrier trapping at the sharply
resolved Coulomb potential wells generated by
the ionised discrete random dopants. In order to
30
remove this artifact, the DG approach is
employed as a quantum correction technology Fig. 4(a): Structure of the simulated 45nm LP
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for both electrons and holes. The LER illustrated technology transistors, nMOSFET on left,
.eur in Fig. 2(a) is introduced through 1D Fourier pMOSFET on right
oasiasemiconductor
synthesis and random gate edges are generated
from a power spectrum corresponding to a
Gaussian autocorrelation function, with typical
correlation length 30nm and RMS amplitude 1.3
nm, which is the level that is achieved with
current lithography systems.
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The procedure used for simulating PGG
involves the random generation of poly-grains
for the whole gate region: a large AFM image Fig. 4(b): Agreement between the commercial
square4
Issue II 2009
of polycrystalline silicon grains illustrated in Fig. TCAD and the University of Glasgow’s ‘atomistic’
3(a) has been used as a template and image is simulator results, nMOSFET on left, pMOSFET
scaled according to the experimentally observed on right
average grain diameter through X-Ray-
diffraction measurements (the average grain
diameter is 65nm). Then the simulator imports a
random section of the grain template image that
Below: Fig. 3(a): corresponds to the gate dimension of the
SEM micrograph of simulated device and along grain boundaries,
typical PSG (10) the applied gate potential in the polysilicon is
modified in a way that the Fermi level remains
pinned at a certain position in the silicon
bandgap. In the worst case scenario the Fermi
level is pinned in the middle of the silicon gap.
The impact of polysilicon grain boundary Fig. 4(c): Potential distribution in one of the
variation on device characteristics is simulated simulated 200 microscopically different
through the pinning of the potential in the characteristics in the presence of RDD, LER and
polysilicon gate along the grain boundaries. PSG, nMOSFET on left, pMOSFET on right
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