Intellectual Property
both model and design with. What is more, those companies that sell IP to
It is true that device matching is in itself by systems houses need to ensure that their
no means a new issue. Analogue designers have products can not only function but also provide
been aware of the need to mitigate variation economic yield within one, or perhaps several
effects for decades. What is new is that digital different foundries. What this means in reality
groups now need to be aware of this within DSM are tuned designs for different flavours of
since this can and does have big effects upon process...Nothing new here for the analogue
critical timing paths. guys reading this, but it is pretty much new
Now consider embedded RAMS as an ground for the new breed of digital engineers.
Issue VII 2009
extreme case since these are typically small Compound this by adding up the costs
square4
dimension, tightly packed structures which will associated with commissioning a working design Tony Harker
.com
test any process for both systematic and random and then apply that to a typical VC or Angel Graduated in 1983
effects. At a recent NMI conference on variability funded start-up and it’s not difficult to see the and has held
held in London. problems. product engineering,
Dr Kelin Kun of Intel showed a slide which The big IP companies, and IDMs that use IP design engineering,
brought the issue home for me. A 32nm RAM flows can afford to use the newest tools to get design centre
cell was shown to be 0.171 µm2 . Now compare the job done properly. They also (usually) have management,
that to a 1980’s RAM cell at 1700µm2. That the clout within foundries to get what they need project management
oasiasemiconductor
equates 0.01% of the original area! Indeed, the from the process guys. Applying this model to and director level
.eur
32nm RAM cell can fit a hundred fold into a the start-up or SME IC Fabless outfit is clearly roles at a senior level
www
single contact well on the 1980’s process. The Vt not so simple. with a number of
issues really hit hard in the smaller process The entry bar for IC design was already set multinational IC
19
geometries which are also compounded by the at a high level – even before we got to 90nm companies including
www
natural drive towards lower operating voltages. and below. Smaller companies can only National
.eur As Vmin and the threshold voltages realistically make progress by close relationships Semiconductor,
oasiasemiconductor
converge device function becomes a difficult with key foundries and EDA companies. Test Fujitsu and Cypress
thing to both control and model. Indeed it used chips are almost mandatory so MPW and other Semiconductor. Most
to be that RAM yield was primarily driven down wafer sharing options are commonly used to test recently and until
by particle or hard faults. devices. Even then smaller companies need to April 2009 Tony was
Whilst the major foundries are doing depend upon models and checking decks which CEO of iSLI, a
everything they can to mitigate these risks, it is accurately represent the target technologies. collaboration in
.com
fair to say that nowadays RAMS are likely to Foundries and large IDMs can invest in some of System Level Design
malfunction in 45nm or below due to soft fails this research themselves, and indeed do as Capability and
caused by inherent variability within the process. evidenced by material from Intel, ARM, IBM, ST, Education by four of
square4
Issue VII 2009
So the activities of the designer and the Chartered and Altera at the 2009 NMI Variability Scotland’s leading
process or device engineer are overlapping to Conference. universities designed
the extent that IC and IP designers are now So we have to consider the IP landscape as to enhance the
required to know a lot more about process being two tier, the top tier or Super league will industry/academic
variation and yield drop-out mitigation than ever be dominated by IDMs and large scale IP houses interface.
before. who can afford the overheads to ensure IP in Tony, a regular
The challenges offered by modern DSM 45nm and below yields at economic levels. The contributor to
design is proving to be be a major catalyst for second Tier will be much smaller. Populated by various publications,
research by the leading EDA vendors. Tools are niche based companies who concentrate upon now runs his own
emerging which can cover the main bases with high value bespoke solutions, which are in turn consultancy business
functions to include variation aware parasitic backed by investors with deep pockets and long specializing in
extraction, smart DRC checking suites which can term outlooks. helping technology
take into account planarity, fill functions, effects From my perspective I cannot see many based companies
of CMP and all sorts of OPC related effects. This small companies, providing IP in ultra DSM in from his home close
is great news in that it helps mitigate those risks. the next few years. I may of course be wrong, to Stonehenge in
It does however mean that everyone in the but there is a distinct chance that UDSM IP Wiltshire, United
business needs to use these tools to stand a may become the exclusive realm of the Kingdom.
decent chance of attaining a working design. Super league.
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