Intellectual Property
it right first time has never been greater. Driven conversation to today it would be similar in tone
primarily by revenue windows and mask costs, but would cover a lot of new ground
the associated development bill is coming under including....How do you mitigate DSM
ever closer scrutiny. For the past couple of lithography effects to ensure maximum yield
decades companies have looked to advanced across all foundry processes? How do you
tools and latterly the use of pre-designed and account for Vt and parasitic variations across the
tested IP to mitigate the inherent high risks. All die to ensure timing margins are met in all
of this makes perfect sense and has rightly process corners? How do you minimize
provided good business for the big names in systematic error rates within the embedded
Issue VII 2009
EDA and IP. It is however worthwhile pondering RAMs?
square4
the plight of IC start-ups and how life is for them There are two main sources of error built
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in trying to build an effective DSM IP business in into any system. These can be broadly
today’s market. categorized as systematic and random. There is
Back in the eighties I remember discussions little we can do about random effects, statistical
with a company (who were selling soft IP) along analyses tells us there is a finite chance of things
the lines of …. OK so you say this is a UART and happening. The effects of which may vary
that it works fine. You also provide fault depending upon what and where it happens. On
coverage vectors to check “stuck at” faults. the other hand, systematic errors can be linked
oasiasemiconductor
These will make sure that any faults in my back to specific causes and therefore action can
.eur
process can be found at wafer sort. All of this is be taken to minimize the risks and therefore the
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great but ….how can you prove to me that the associated fallout.
18
UART works functionally within my system whilst
I am developing it? In other words, do you have Diagram Random and Systematic
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a functional model for me to design with? errors (bell curves)?
.eur If we transpose this IP In DSM today, variation across die needs to
oasiasemiconductor
be treated very seriously since this can
cause catastrophic variation in
timing and ultimately result in
functional errors. Variation in
implant doses within and
between individual
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channels did not seem
too important in the
days of +100nm.
square4
Issue VII 2009
However when we
consider that there
may be only a few
hundreds of dopant
atoms in any one 45nm
channel then the effects
can be amplified
enormously. Doping
densities can vary across
individual transistors due to
non linear dopant population
and transistor to transistor variation
can differ according to topography. Add
the effects of varying Gate Oxides (at 45nm
Tox may only be 2 or 3 molecules thick), Critical
Dimensions of the gates due to optical effects
and interconnect contact and via resistances and
we now have a multidimensional problem to
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