Compatibility of polymers and fluxes: Getting to the heart of the matter
ing or adhesion.
power semiconductor die-attach
Failure modes
For many years, a typical power semicon-
ductor assembly process has involved the
process steps shown in Figure 2.a. The use
of wire bonding in the assembly process as a
final step has meant that high cleanliness of
the bond pads is essential
5
, and it was previ-
ously believed that a no-clean process was
not feasible. However, replacing wire bond-
ing with clip-attach processes for simple
P/N devices, as shown in Figure 2.b, we now
have a situation where a no-clean process is
not only feasible but also desirable, because
it eliminates the costly cleaning step.
The main potential failure modes for
no-clean processing here are:
Electrical—Figure 3 shows a photo-
graph of the top junction of a simple
P/N (single junction) device with its
metallization, as used in a clip-bonding
assembly process with no-clean solder
Figure 5. A no-clean clip-bonded component immediately before encapsulation.
paste. Figure 4 shows the structure of the
device. As seen in Figure 4, the thin sili-
con dioxide electrical barrier is the only
Figure 5 is a picture of a no-clean clip-
references
thing standing in the way of current
bonded component manufactured in high
[1] “The Evolution Revolution—Flux Usage
leakage between the P and N junctions
volume by a large Asian power semicon-
in Semiconductor Packaging” Mackie,
of the semiconductor.
ductor manufacturer immediately before
Hisert, Low—Advanced Packaging
encapsulation (final step in Figure 2.b).
(September 2007)uote “No-clean is a
Delamination—It is theorized that the process, not a material,” Private Com-
incompatibility of molding compounds conclusion munication to Andy Mackie from Doug
with no-clean flux residues can possibly Although hampered by a lack of industry- Hillman, Rockwell Collins, Nepcon
lead to failure. However, it has been standard test methods, many parts of the West, 1999.
found that as long as the residue level is electronics assembly and semiconductor [2] “Conformal coating issues: When reli-
low, this is not a cause for concern. assembly industries are moving toward no- ability goes astray” Schweigart, Global
clean processes based on in-house test meth-
SMT and Packaging 7.3 (March 2007)
Test methods ods. The development of materials with [3] “Qualification and Performance of
Interestingly, there are no known standards benign, ultra-low residues is a key factor to Electrical Insulating Compound for
in power semiconductor assembly that success. This trend will clearly continue into Printed Wiring Assemblies” IPC-CC-
address issues with no-clean flux-based the foreseeable future. 830B (August 2002)
processes and encapsulation or molding [4] Clip Bonding
compounds. Extrapolation from standard acknowledgements [5] “Surface Insulation Resistance, Fluxes”,
IPC SIR test data is fraught with complica- The authors would like to acknowledge the IPC-TM-650:2.6.3.3 (June 2004)
tions, as the operating voltages of power contribution of Mike Fenner and Jim Hisert
devices are typically many times greater than of the Indium Corporation Global Techni- Dr. Andy Mackie is product manager for
the 45-50V bias voltage and -100V test volt- cal Service team for useful discussions. Indium’s Semiconductor Packaging Materials.
age used in the IPC test method
6
.
However, several manufacturers in Asia Christopher Nash is a technical support
have now qualified solder pastes for use engineer with Indium Corporation.
in power semiconductor clip-bonding ap-
plications, based on testing accelerated life.
Testing has focused on:
• Minimum over-voltage readings and
their change over several months under
high temperature and humidity condi-
tions, known as accelerated life testing
(ALT).
• Observation of the delamination of
molding compounds from flux residues
as studied by cross-sectioning after ALT.
22 – Global SMT & Packaging – September 2008 www.globalsmt.net
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