NEWS DESK
7
ARM announces industry’s first
SOI physical IP library
ARM announced the industry’s first director, Semico Research Corp. To date, them and others to ensure the
Silicon on Insulator (SOI) physical IP two major barriers have inhibited the semiconductor industry can reach new
library including standard cell, memory broad adoption of SOI as this alternative, milestones in the battle for more power
and I/O libraries for IBM’s fully enabled foundry capacity and IP library efficient products.”
45nm SOI foundry, also announced today. availability. Two years ago, Soitec and ARM
As lower power levels and increased With the announcements, ARM and announced a joint agreement supporting
system on chip (SoC) performance IBM have together taken the first step the development of SOI libraries for the
become more difficult to achieve with a toward breaking down these barriers and fabless and foundry arenas, promising
traditional bulk CMOS process, SOI making SOI a viable alternative for many designers a solution to accelerate SOI
technology enables up to 30 percent more applications in networking, storage, adoption and design, explained Andrè-
better performance and 40 percent power communication and consumer Jacques Auberton-Hervè, president and
savings at existing process nodes. applications. CEO, Soitec. Today’s announcement
The ARM SOI library of physical IP is Tom Lantzsch, vice president of marks a significant milestone in
the only design platform of its kind in the marketing for the ARM physical IP delivering our promise of reducing the
industry and promises to significantly division said, ”The delivery of our barriers to entry by developing the design
ease implementation of SOI technology physical IP libraries in support of the infrastructure critical to the fabless and
and bring the benefits of this emerging industry’s very first fully enabled SOI foundry communities.
process to a much wider range of foundry is a testament to ARM’s heritage The ARM SOI physical IP library is
semiconductor companies. of collaboration to remain at the forefront supported by standard synthesis and place
As semiconductor vendors continue in of technical innovation in the and route implementation flows which
the race toward higher speeds and lower semiconductor industry. Our strong enable customers to quickly implement
operating power, an alternative to partnerships with industry leaders like products without changing design
traditional bulk CMOS technology is IBM and Soitec continue to serve as the methodologies or training of employees.
critical to the continued evolution of the cornerstone of our business model and we EDA views for Synopsys, Cadence and
industry,” said Joanne Itow, managing look forward to working in tandem with Magma tools are supported.
‘design to manufacturing’ collaboration
Fujitsu Microelectronics, e-Shuttle
will facilitate a unique capability for
virtually maskless ICs that will increase
and D2S to develop maskless ICs
design starts. Enabling the long tail of
ASIC designs, particularly for derivative
designs, is beneficial for the
FUJITSU MICROELECTRONICS (FM), ICs) continue to shrink, with future semiconductor industry overall.”
e-Shuttle and D2S announced an profitability of many applications “e-Shuttle has been in operation since
agreement under which FM and e-Shuttle anticipated to be threatened. Without the November 2006 with the mission to bring
will adopt D2S’ advanced design for e- need to rely on a lithography EBDW capabilities to low volume
beam (DFEB) technology, starting with a breakthrough, D2S’ advanced DFEB production applications. This
65 nm low power (LP) library, to result in technology maximises and enhances the collaboration further increases the
the creation of test silicon to refine and existing e-beam technology from throughput of our production line,” said
validate DFEB technology for the 65 nm, Advantest. By efficiently employing the Haruo Tsuchikawa, CEO of e-Shuttle,
40 nm and below nodes. e-Shuttle will EBDW approach, DFEB technology “We view this collaboration between
produce test chips using D2S’ advanced eliminates the cost of masks and can design software, design, manufacturing,
DFEB design and software capabilities, speed time to market by shortening the and equipment makers to be essential for
and FM’s standard cell libraries. ‘design to lithography’ process flow. This maximising the capabilities of today’s
These test chips will be manufactured type of DFEB technology can impact fabrication technologies.”
using Advantest’s e-beam direct write specific application fields, such as “The increasing cost of masks is
(EBDW) lithography equipment, which is computing, as well as a host of low to mid making low volume of custom ICs
already in operation at e-Shuttle. As a volume semiconductor companies economically infeasible yet, in aggregate,
result of this partnership, FM will be able producing test chips, engineering samples this segment can represent as much as the
to manufacture ICs faster and cost and design derivatives. high volume segment,” said Aki Fujimura,
effectively than is possible with “We are uniquely positioned with e- founder and CEO of D2S. “This long tail
conventional e-beam direct lithography. Shuttle as the leader in manufacturing of the custom IC business can be enabled
The rising cost trends of advanced ICs chips using the DFEB approach,” said through a virtually maskless DFEB
show no signs of slowing unless a new Yoji Hino, corporate executive vice technology. By not requiring the
manufacturing approach is adopted. president of Fujitsu Microelectronics. development of any new hardware
Especially with mask budgets doubling at “We expect to see the benefits of this technologies, this design and software
every node, the application range and collaboration, in terms of reduced costs approach represents a low risk, low cost
market for low volume ASICs (custom and time savings, starting in 2009. This path to a new production paradigm.”
November 2008 www.euroasiasemiconductor.com
Page 1  |  Page 2  |  Page 3  |  Page 4  |  Page 5  |  Page 6  |  Page 7  |  Page 8  |  Page 9  |  Page 10  |  Page 11  |  Page 12  |  Page 13  |  Page 14  |  Page 15  |  Page 16  |  Page 17  |  Page 18  |  Page 19  |  Page 20  |  Page 21  |  Page 22  |  Page 23  |  Page 24  |  Page 25  |  Page 26  |  Page 27  |  Page 28  |  Page 29  |  Page 30  |  Page 31  |  Page 32  |  Page 33  |  Page 34  |  Page 35  |  Page 36  |  Page 37  |  Page 38  |  Page 39  |  Page 40  |  Page 41  |  Page 42  |  Page 43  |  Page 44  |  Page 45  |  Page 46  |  Page 47  |  Page 48  |  Page 49  |  Page 50  |  Page 51  |  Page 52  |  Page 53  |  Page 54  |  Page 55  |  Page 56  |  Page 57  |  Page 58  |  Page 59  |  Page 60  |  Page 61  |  Page 62  |  Page 63  |  Page 64  |  Page 65  |  Page 66  |  Page 67  |  Page 68