RESEARCH NEWS
19
Main picture: A view into IMEC’s
to the charge based Flash devices, and processor can be completely programmed 300mm clean room
potentially small cell size. RRAM is seen in a high level programming language (C)
as a potential candidate to replace and compiled with the DRESC compiler, Inset: Stretchable LED circuit
conventional Flash memory and hence to included in the license. embedded in PDMS, fixed on textile,
push non volatile memory technology and washed repeatedly in a standard
towards the (sub )22nm technology node. Thinner solar control washing machine
IMEC’s research activities on RRAM IMEC presented their progress for
mainly focus on investigating the photovoltaics (PV) and affirmed the belief
switching behaviour of the RRAM cell that silicon based PV provide the most of the tool box at their disposable
concept that uses metal oxides as a realistic solution for at least the next includes alternative back side dielectric
switching element, and on demonstrating decade and focus their attention on passivation layers, selective doping of
its scaling capability down to 25nm. This reducing cost of manufacturing while emitter and back surface contacts,
will be achieved by concentrating on three improving performance. According to metallisation technologies, and
areas being RRAM stack optimisation, IMEC the amount of Silicon that is used interdigitated back side contacts (i-BC).
RRAM cell scaling and RRAM per Wp (peak Watt) should be reduced by IMEC also explores wafer based bulk
integration in a crossbar RRAM array. at least a factor of 2. And the efficiency silicon solar cells, silicon thin films,
IMEC also announced that Toshiba of the solar cells should be increased by compound materials and organics.
had licensed their ADRES reconfigurable 25%, going from 16% to over 20% for Hasselt University is home to IMEC’s
processor template, the DRESC compiler, industrial crystalline Si solar cells. There associated laboratory IMOMEC where a
and the MPSoC (multi processor system is also the need to be able to produce new method has been developed to
on chip) suite of design tools. ADRES components, such as metallisation layers, stabilise the nanomorphology of organic
(Architecture for Dynamically surface and contact passivation more solar cells resulting in a lifetime
Reconfigurable Embedded Systems) is a efficiently and with cheaper materials. improvement of at least a factor 10. With
processor architecture designed for Overall IMEC believes that the cost of these stabilised solar cells, efficiencies
wireless and multimedia processing in generating electricity from PV needs to were achieved comparable to state of the
single and multiprocessor systems. come down by a factor of 5. art organic solar cells. This potentially
ADRES processors are suited for future And although other options than paves the way to commercial organic
mobile terminals, such as software crystalline Si are investigated, the R&D solar cells with an operational lifetime of
defined radios. MPSoC is a suite of tools on crystalline Si solar cells still forms a over 5 years and efficiencies of over 10%.
to help build and map applications for major part of IMEC’s photovoltaic Stabilising the mix of organic compounds
multiprocessor platforms. Through an research. IMEC aims to reduce the active that can trap the light’s energy and
XML template, designers can create the silicon layer thickness from 150µm today transport it to an electric contact
ADRES processor instance that is best down to 40µm in 2020 as well as improves the efficiency and operation of
suited. And applications for an ADRES achieving efficiencies of up to 20%. Part organic solar cells.
November 2008 www.euroasiasemiconductor.com
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