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RESEARCH NEWS
Another new dimension IMEC presented results in device
IMEC announced significant progress manufacturing using EUV lithography
with its 3D-SIC (3D stacked IC) including the recently announced
technology. They reported a first time functional 0.186µm
2
32nm SRAM cells
demonstration of 3D integrated circuits made with FinFETs. IMEC has also
obtained by die to die stacking and using completed the integration and site
5µm Cu through silicon vias (TSV). The acceptance tests of the EUV Alpha Demo
dies were realised on 200mm wafers in Tool in its 300mm research facility which
IMEC’s reference 0.13µm CMOS process has paved the way for the current results
with an added Cu-TSVs process. For for IMEC and its partners. There are a
stacking, the top die was thinned down to number of main issues for EUV
25µm and bonded to the landing die by lithography including resists, optics,
Cu-Cu thermocompression. photomasks, throughput and source. The IMEC from the sky
The cost of 3D approaches is impacted most pressing need is a reliable high
most by the capital equipment cost, with power source that needs to be increased IMEC is involved in numerous EC co
silicon etching, copper filling and die to from 120 W to 170 W and then toward funded research projects that help
wafer bonding being the main areas where 250 W. Throughput is directly impacted improve European competitiveness. IMEC
improvements are required. by the source power and IMEC currently continues to be strongly involved,
To evaluate the impact of the 3D SIC flow puts EUV throughput at 4 wafers per although it hopes the budget for the
on the characteristics of the stacked hour. Just under the expected 6 at this programme will be increased. The
layers, both the top and landing wafers stage of the development and still a long comments were more directed towards the
contained CMOS circuits. Extensive tests way from practical manufacturing levels. Eureka funded programmes.
confirmed that the performance of the IMEC report positive progress on all “Eureka’s goal is to stimulate cross
circuits does not degrade with adding Cu other areas of concern and are hoping border collaboration to improve the
TSVs and stacking. To test the integrity that a proposed improved source at the economic prosperity of Europe and to
and performance of the 3D stack, ring end of 2008 will produce significant reinforce the ability of the European
oscillators with varying configurations results. Both IMEC and ASML expect industry to be at the forefront of global
were made, distributed over the two chip Beta tool availability in 2010 but no competition. This matches our vision of
layers and connected with the Cu TSVs. manufacturing until at least 2012. helping to guarantee a competitive
Tested after the TSV and stacking ASML also revealed the latest version position in a global market,” said
process, these circuits demonstrated the of their lithography platform called the Declerck. “Therefore, we expect a lot
chips excellent integrity. Eric Beyne, TWINSCAN NXT. Unashamedly a bridge from Eureka and like programmes.
IMEC Scientific Director for 3D tool between immersion and EUV, most of However, at this moment, Eureka is only
Technologies stated that they are now the advances on the new platform were a funded locally, with funds which are
ready to accept reference test circuits direct result of work on the EUV platform mainly meant to support local players
from industry partners. and focused on improvements in overlay within a country or a region, not to
and productivity. The TWINSCAN NXT stimulate cross border collaboration
Litho inches forward features a new planar wafer stage design. between e.g. research organisations in one
This particular trip was coupled with a The wafer stage is lighter than previous country and companies in another
visit to ASML and the thrust of the with new materials and designs in play country. But as the market and the
IMEC discussions were in line with enabling high acceleration for shorter competition has become global, research
ASML in declaring extreme ultraviolet positioning times. The platform is centres must work together with
lithography (EUV) as the most probable expected to initially improve productivity companies worldwide and borders should
manufacturing method at 22nm and by more than 30 percent. An overlay not create limitations. Therefore, we call
below manufacturing. Kurt Ronse, improvement of 50 percent is claimed Eureka to set up the means to stimulate
director of the advanced lithography with a new positioning measurement collaboration with appropriate cross
discussed how immersion lithography was system up to 2 nm. They expect the new border funding schemes.”
unlikely to meet industry needs due to an tool to increase wafer output from 100 According to IMEC the only way to
inability to find the appropriate materials. wph to 250 wph. increase Europe’s microelectronics
competitiveness is for Europe and its
IMEC fires European salvo governing public authorities to stimulate
As the leading European independent true cross border collaborations, not only
research centre, IMEC is integral to by setting up networks but also by
many joint efforts across Europe. So creating the financial means. Only
when Gilbert Declerck, CEO of IMEC international collaboration will enable
states a lack of international outlook for Europe to continue to play a competitive
EU funded directives such as Eureka were role in nanoelectronics and related fields.
of little use to IMEC then the powers that IMEC has come along way as it heads
be behind the EU programmes should into its 25th year. Today IMEC is
Test-chip taped for assessing design ensure they remain relevant to the global regarded as one of the leading research
rules and models for 3D-SIC market and ensure positive growth for the centres worldwide in this field and a true
technology European region. example of ‘open innovation’.
www.euroasiasemiconductor.com November 2008
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