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26
DEPOSITION
(a-Si) layer, on top of SiO
2
, was etched completely and
uniformly. All the obtained oxide etch rates and oxide etch non
uniformities of the Ar/N
2
/F
2
cleaning gas mixture on SiO
2
are
equal or better than the standard CF
4
based BKM (Best Known
Method) chamber clean of Applied Materials. The Ar/N
2
/F
2
etching rate of amorphous Si was tested, resulting in etch rates
of > 1200 nm/min.
The superior etch rate performance of Ar/N
2
/F
2
gas mixture
was combined with excellent etch non uniformities values. On
Figure 5: View inside the AMAT P5000 chamber lid after the SiO2 the Ar/N
2
/F
2
gas shows a very low etch non uniformity of
repeatability of SiO
2
deposition and Ar/N
2
/F
2
gas cleaning ±3 (1sigma) and on Si
3
N
4
of ±8% (1sigma), respectively. This
runs (total 75 wafers) with the Susceptor and creamed data were achieved for a total of 75 wafers, within as well as
coloured large and small O-rings (a.) as well as the wafer to wafer, demonstrating a very repeatable and stable oxide
shower head (b.). etching rate. The etch non uniformity of C2F6/O2 with ±10%
(1sigma) and NF
3
with ±9% (1sigma) are significant lower
compared to Ar/N
2
/F
2
.
Conclusions The particle performance data of the Ar/N
2
/F
2
cleaning gas,
In this work, an Ar/N
2
/F
2
gas mixture was used with 10% Ar, showed in average just 14 particle adders (0.25µm) generated
20% F
2
and 70% N
2
in order to obtain a maximum of 20% from run to run. The data indicate that no significant particle
fluorine as inert gas. The evaluation of the Ar/N
2
/F
2
gas mixture contamination was induced by the process and Ar/N
2
/F
2
can very
was performed in a 200mm Applied Materials PECVD reactor well be used as a high performance clean etching gas. The tested
on a P5000 main frame. The etch rate and etch non uniformity, mixture Ar/N
2
/F
2
shows improvements in both parameters,
of Ar/N
2
/F
2
on SiO
2
and Si
3
N
4
, respectively, was tested on cleaning at a faster rate, even requiring a lower amount of gas.
standard CVD cleaning gases, like NF
3
, CF
4
and C
2
F
6
/O
2
. The Particularly, the NF
3
cleaning method requires, for SiO
2
repeatability (total 75 wafers) of the Ar/N
2
/F
2
etch rates on SiO
2
processes, a longer cleaning time (+27%) and almost the double
within wafer, wafer to wafer and batch to batch as well as the amount of process gas (+196%). The high etching rate of the
particle performance, has been performed. selected Ar/N
2/
F
2
mixture and the low gas requirement indicate
The highest etching rates of all gases (NF
3
, C
2
F
6
/O
2
, CF
4
) are that a significant Cost of Ownership reduction can be achieved,
achieved by Ar/N
2
/F
2
mixture of 1216 nm/min for SiO
2
and both increasing the tool throughput and reducing the
1850 nm/min for Si
3
N
4
. The Ar/N
2
/F
2
cleaning gas mixture consumables requirement, in comparison with the CF
4
and NF
3
achieved a higher cleaning rates for dielectric films, like SiO
2
based cleaning chemistries that have been tested.
and Si
3
N
4
compared to the standard CF
4
cleaning recipe and an These results have been achieved with a cleaning chemistry
optimised NF
3
chamber clean. Also a 300nm amorphous Silicon with GWP=0. F
2
mixtures are available world wide in standard
cylinders from Solvay Fluor.
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Pittroff, “Feasibility Study for Usage of diluted Fluorine for Akira Sekiya, “Evaluation of fluorine gas as an alternative PE-
Chamber Clean Etch Applications as an Environmental Friendly CVD chamber cleaning chemical”, Research Institute of
Replacement of NF
3
”, Materials Research Society, Volume 914, Innovative Technology for the Earth (RITE) and National
pp. 445, Paper #0914-F09-23, 2006. Institute of Advanced Industrial Science and Technology (AIST),
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and environmental issues”, Gases and Technology, Hage, “On-Site Generation of High Purity Fluorine as a Safe
September/October 2003. and Economical Alternative for CVD Chamber Cleaning” Future
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installed-base CVD tools”, IEEE/ SEMI Advanced Myers, Susan Orneals and Joe Van Gompel, “Integrated fluorine
Semiconductor Manufacturing conference, April 2005. supply strategy for CVD chamber cleaning applications”,
[4] Walter F. Worth, “Achieving sustainability in the Semiconductor Equipment and Technologies (ISBN # 1-
semiconductor manufacturing industry”, International Sematech 882688-78-4), 2002.
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[5] Oliver F. Schedlbauer and Hubert F. Winzig, “Cost “Improving Thermal cleaning process”, Euro Asia
reduction challenges in CVD chamber cleaning: strategies to Semiconductor, April 2007
reduce gas”, Future Fab Intl., Volume 13, July 2002. [11] Robert Wieland, Handbook of 3D Integration , Vol. 1,
[6] Andrew D. Johnson, William R. Entley, Peter J. Maroulis, chapter 6, ,”SiO2”, edited by P. Garrou/ C. Bower/ P. Ramm,
“Reducing PFC gas emission from CVD chamber cleaning”, (978-3-527-32034-9), to be published in June 2008.
Acknowledgement:
The authors would like to acknowledge Trelleborg Sealing Solutions GmbH (Stuttgart, Germany) for the delivery of excellent F2
resistant O-ring seals (Isolast 9675).
www.euroasiasemiconductor.com August 2008
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