THROUGH SILICON VIAS
17
Alchimer approach to
TSVs cuts CoO by 50%
The company has developed the enabling technology to make high
aspect ratio TSVs, economically. Steve Lerner, CEO, explains the
company’s electrografting technology which creates conformal layers
with excellent step coverage and can eliminate expensive vapour
deposition processes from TSV metallisation.
By Steve Lerner, CEO, Alchimer
T
he ability to build through functioning of the filled via, three layers
silicon vias (TSVs) of material must be deposited. The first is
economically is essential to an isolation layer to electrically separate
the adoption of 3D IC packaging, in the body of the silicon in the die from the
which semiconductor die are vertically copper inside the TSV. The second is a
stacked in order to drastically reduce barrier layer which prevents copper
their footprint. 3D IC packaging promises diffusion into the silicon. Both of these
reduced size, cost and power layers are essential for the correct
consumption, while increasing both functioning of the device. On top of these
functionality and performance. However, is a thin layer of copper called the copper
the limitations of vapour deposition seed layer. It’s critical for the subsequent
processes have been holding back electroplating process that the copper Figure 1: A conformal electrografted
progress in this area. Alchimer’s seed layer is continuous, otherwise voids copper seed layer over high aspect
technology by far surpasses the will form in the copper fill, which ruins ratio TSVs
performance capabilities of PVD, and the via.
cuts the cost of ownership of TSV So far the deposition of these three
metallisation by 50% overall. layers has utilised dry vapor deposition
A TSV is an electrical connection processes such as PVD and CVD. These
between die. Typical methods of vapor deposition processes can produce
constructing TSVs involve etching a long, TSVs comfortably up to 3:1 aspect ratio
thin hole (a via) through the die and (AR). Bearing in mind that the ITRS and
filling it with copper. There are various Sematech roadmaps call for 10:1 AR vias
steps in this process. Techniques for immediately, it’s fair to say that these
etching the via include laser drilling, processes have caused something of a
DRIE (deep reactive ion etch) and ‘Bosch’ bottleneck in the development of TSV
DRIE for deep vias. Filling the via with technology. Since PVD is a line of sight
copper is done by electroplating, a long- process, it is totally unsuitable for
understood process that applies an depositing material on TSVs that have
electrical current to the substrate vertical sidewalls, and they are pretty Figure 2: A conformal layer of copper
immersed in a bath containing copper hopeless at creating continuous layers electrografted to scalloped TSV
ions. Between the etch and copper fill over the ‘scalloped’ sidewalls created by sidewalls that was deposited using
steps however, to ensure the correct Bosch etching. Techniques such as ionised Alchimer’s eG ViaCoat process
August 2008 www.euroasiasemiconductor.com
Page 1  |  Page 2  |  Page 3  |  Page 4  |  Page 5  |  Page 6  |  Page 7  |  Page 8  |  Page 9  |  Page 10  |  Page 11  |  Page 12  |  Page 13  |  Page 14  |  Page 15  |  Page 16  |  Page 17  |  Page 18  |  Page 19  |  Page 20  |  Page 21  |  Page 22  |  Page 23  |  Page 24  |  Page 25  |  Page 26  |  Page 27  |  Page 28  |  Page 29  |  Page 30  |  Page 31  |  Page 32  |  Page 33  |  Page 34  |  Page 35  |  Page 36  |  Page 37  |  Page 38  |  Page 39  |  Page 40  |  Page 41  |  Page 42  |  Page 43  |  Page 44