News & McLean vFinal DR 2/3/10 16:35 Page 7
Company News
TSMC and MAPPER reached joint
development milestone
TSMC and MAPPER Lithography have TSMC Senior Vice President of Research
revealed that a pre-alpha MAPPER tool & Development.
located on TSMC’s Fab 12 GigaFab is “The results coming from our
repeatedly printing features previously project with MAPPER have met
unachievable using current immersion aggressive objectives and mark a
lithography technology. Over the past significant achievement in our Multiple-
several months TSMC has expanded its E-Beam Direct Write program that
Maskless Lithography team and has covers all viable Multiple-E-Beam
been working with MAPPER engineers technologies. Based on these
at Fab 12 to integrate electron beam encouraging results, we are convinced
Issue I 2010
direct write capabilities into that the Multiple-E-Beam technology is operational tool at TSMC and we
square4
manufacturing processes for one of the technologies to become the simultaneously intensify our efforts in
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development of future technology future lithography standard.” bringing MAPPER’s technology to
nodes. Dr. Christopher Hegarty, MAPPER’s market, we are supremely confident
“TSMC is always searching for the CEO adds, “Having TSMC as our launch that electron beam direct write will be
most cost effective manufacturing customer is of great benefit to successfully introduced into high-
processes,” says Dr. Shang-Yi Chiang, MAPPER. Now that we have an volume manufacturing processes.”
oasiasemiconductor
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Tera-scale joint venture for future memory
www
INTEL is teaming up with Glasgow University to facilitate the “We hope this project will result in new chip design
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design of future nanoscale memories with a European paradigms for building reliable memory systems out of
taskforce has been set up to investigate how to design the unreliable nano-scale components cheaply and effectively,
next generation of tera-scale computer memory systems. heralding the era of tera-scale computing.”
Within the next decade microchips are expected to Central to the project is simulation software developed
incorporate billions of transistors, the tiny on-off switches by Prof Asenov in an earlier £5.3m Engineering and Physical
that enable circuits to process and store data, creating ultra- Sciences Research Council eScience pilot project called
powerful computer systems that can process trillions of NanoCMOS. The NanoCMOS simulations use grid
bytes (terabytes) of data per second. computing, which utilises the processor power of thousands
The ‘Tera-scale Reliable Adaptive Memory Systems’ of linked computers, to simulate how hundreds of thousands
(TRAMS) consortium includes: Intel Corporation Iberia, of transistors, each with their own individual characterstics,
Interuniversitair Micro-Elektronica Centrium vzw, the will function within a circuit.
University of Glasgow, and the Universitat Politecnica de Prof Asenov and the University of Glasgow is setting up
Catalunya, and is financed through the EU’s Framework a company called Gold Standard Simulations to exploit this
Programme 7 (FP7) science research fund. technology which will be critical to the work of the TRAMS
Professor Asen Asenov, of the Department of Electronic project, with all device design and simulation work being
and Electrical Engineering is leading the University of conducted at Glasgow.
Glasgow’s involvement at the heart of the project. He is a In investigating design possibilities for future
world leading authority on the variability of Complementary microchips, the team will focus on future generation of
Metal-Oxide Semiconductors (CMOS) transistors and CMOS microchip technologies – which comprise transistors
microchips and has researched this field for many years. less than 16 nanometres in size (by comparison a human hair
He said: “Tera-scale computing will transform the is around 100,000 nanometres wide).
power, performance and functionality of personal The transistors will be design and simulated exclusively
computers, phones and other electronic devices as well as by Glasgow. The TRAMS consortium will also consider what
large computing facilities such as data centres. are known as ‘Beyond CMOS’ technologies; nanowire
“However, if we are to continue to shrink the size of transistors, quantum devices, carbon nanotubes and
transistors in order to develop such powerful circuits in the molecular electronics, which are expected to be as small as
future, we need fundamentally new approaches to circuit five nanometres.
and system design that can take account of the variability The project is expected to last three years.
within transistors.
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