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DESIGN FOR MANUFACTURING
critical paths where high speed is
necessary, allowing designers to
assign faster transistors on those
paths and use slower but less power
In addition to designing for greater variability, developers should hungry transistors elsewhere. In an FPGA where the critical path
begin to incorporate redundancy in order to improve chip yields. is unknown before programming, and in other applications where
This is particularly important for the large die of today’s circuit speed may vary, a more dynamic trade off is necessary.
complex designs. With large die, even a small change in the Reverse back biasing a transistor increases the threshold voltage,
defect density in production can have a major impact on yield. thereby reducing the power. The back bias of the transistors is
Having on chip redundancy allows the design to bypass defects adjusted automatically based on a specific programme to
instead of simply failing. This redundancy needs to be woven into optimise speed and power.
the architecture at the circuit level, however, not added as an
afterthought. Finally, designers will need to address the challenges of mixed
signal design. Many devices now need to incorporate high speed
Another design change for developers to consider is the lowering transceivers. Even for pure digital logic, analogue and high
of circuit power. As process technology shrinks circuits become frequency circuit content is increasing in order to support such
faster and denser and chip power rises in proportion. For many functions as high speed serial I/O. Successful implementation of
applications, however, chip power is a more important concern such functions requires circuit components optimized for high
than performance. Many applications require greater speed analogue circuit design, but their requirements are often at
functionality in next generation chips without greater power odds with the requirements for high speed digital circuit
requirements, and higher performance is only of secondary components. This discrepancy is becoming more pronounced as
importance. process technology scales down.
The traditional approach to lowering power has been to lower the The key to solving this dilemma is working closely with the
supply voltage to offset the greater number of transistors. foundry early in process development to ensure adequate
Transistor threshold levels do not scale with process technology, optimisation of the essential components for high speed analogue
so lowering the supply voltage reduces the margin with which the design. Developers can also populate a significant portion of
transistor operates. Local variations further reduce that margin. their test chips with analogue components to help develop
The lower the supply voltage, the greater the significance of accurate simulation models. Placing one whole channel of a high
predicting and accounting for local variability specifically for speed transceiver on a test chip, for instance, gives an
threshold voltage. opportunity to evaluate the parasitic effects of interconnects,
model on chip resistors, capacitors, and inductors, and see how
Finding the balance well the design will work. This use of test chips allows designers
In addition to lowering supply, designers will have to adopt other to pre define analogue components and have them fully
approaches to reducing chip power. One that Altera has used is characterized to minimise mismatches in the final design.
to trade performance for power both at the transistor, and
architectural levels. Increasing the threshold of a transistor, for Collectively, all these efforts addressing analogue design, power
instance, slows it down but also reduces its leakage current. tradeoffs, local variability, and the use of test chips work
Similarly, increasing channel length slows a transistor but lowers together to help ensure first time success in 40nm design.
its switching current. Numerous other such tradeoffs can be Further, the methods developed to address these problems will be
made at the transistor level. applicable when it comes time to make the next process
migration. New technical challenges will arise, but the
At the architectural level designers can trade performance for methodology provides the opportunities to resolve those
power on each circuit. In an ASIC design this kind of trade off is challenges while keeping costs down and achieving success with
static. Analysing the performance needs of a circuit identifies the first production silicon.
www.euroasiasemiconductor.com October 2008
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