DESIGN FOR MANUFACTURING
21
A 40nm FPGA results in
increased complexity, size
and design costs
final design for less than the price of one production mask set The test chips and their functions during the 40nm
revision. The total mask cost of the test chip program may research and development effort
exceed the cost of one mask set revision, but the design effort
efficiencies gained in areas such as design re-use and early error The data in Table A shows the % of ASIC designs starts
detection can largely offset the test costs. each year by process technology node on the left hand
vertical, according Gartner statistics for 2007 and their
Along with adopting new design methodologies like the test chip projections for the future. Each column totals to 100.
program, developers embracing 40nm technology will need to This shows that the most popular design process node for
enhance their existing methods and their design parameters. % of designs has been 0.13um for quite some time based
Three areas that are particularly important in this process on the facts that 0.13um offers enough integration
generation are process variability, power management, and high density, performance and reasonable NRE costs for the
performance analogue. While these are known problems in majority of designs. 90 nm technology and beyond is
earlier process generations, 40nm technology puts a unique spin expensive, more risky and requires careful power
on them. management. It is not easy to balance ROI for many
ASIC designs. The right axis is Altera Corporation’s
Know your own variables estimates for the total NRE cost for an ASIC at each
Chip developers have long been aware of and accommodated node. These costs include masks, design, test, and
process variability at the chip level. Monte Carlo statistical software development (both labor, software and
simulations guide designers in creating chips that will work hardware costs). As these costs increase so does risk and
properly when its transistors vary as much as three standard development time.
deviations (3 sigma) from the production mean. But these
techniques only address wafer to wafer variations and chip to If this is contrasted to FPGA development, a few years
chip variations within a wafer. In a 40nm process features are so ago when older technology was being used, FPGAs
small that the placement of individual atoms can have a behind the ASIC technology curve. Today FPGAs are
measurable impact. Gate oxides, for instance, are now only a few ahead of the curve and in the future there will be a 3
atoms thick. The dopant in transistor channels can no longer be process node or more process technology advantage. This
considered relatively uniform. Instead the placement more is invaluable for customers who may compare ASIC vs.
closely resembles a dash of salt grains scattered across a plate, FPGA technology for a given design:
as illustrated in Figure 2, where each outlined square is one
random distribution with an expected value of 50 dopant atoms. Examining cost, density, and performance, no
The actual number of atoms (37, 40 and 60 respectively) for comparison can be made between a 0.13um ASIC to 45-
these three trials shows that in addition to having a random nm or 32-nm technology
spatial distribution, the total number of atoms within each With only a small investment in software development
square varies. tools customers can gain access to the latest process
technology
This dependency on individual atomic placement introduces an
unprecedented degree of local variability to circuit behaviours. These products are programmable and are sold to tens of
Robust statistical analysis and modelling tools, which accurately thousands of customers instead of just one specific
account for local variation, will enable designers to optimise customer for an ASIC. FPGAs maintain a better ROI,
their circuits in the presence of local variability. The capability to thus allowing the manufacturer to steadily invest in
accurately model local variation is especially critical for the newer technologies. The ultimate result is more and more
design of high yielding memory and analogue circuits. For designs will migrate from ASIC to FPGA technology
parameters such as standby current, only the total current across taking advantage of time to market, cost, performance,
a die is of value. In this case, local variation above or below the and power while significantly reducing risk and NRE.
average are cancelled out.
October 2008 www.euroasiasemiconductor.com
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