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DESIGN FOR MANUFACTURING
Getting 40nm right at first attempt
The challenges and risks associated with introducing 40nm design and processing have
been more challenging than any previous migration. The challenges are different for
design and manufacturing but the challenges at 40nm and beyond requires greater
communication between both areas. Mojy Chian, Jeff Watt and Richard Cliff of
Altera Corporation discuss how systematic use of test chips and enhanced statistical
simulation are amongst the keys to successfully addressing 40nm challenges
Designers moving to adopt 40nm process technology face shrinks of existing design layouts or new layouts of existing logic
substantial risks. The new process comes with new design designs to see if they function adequately in the new process. The
challenges to address, and the penalty for error is high. Mask results of such tests help teams define their strategy for both
costs grow about 50% each generation and for 40nm are hard and soft design re-use to save development time and cost. If
running over $3 million. Equally important, the cost of the functional problems appear or the block’s performance needs
design effort is growing because of increasing gate count and improvement, designers have an opportunity to make the
chip complexity, and growing more rapidly than mask cost. necessary changes early in the project. Blocks that traditionally
Designers, then, need to adopt methods that will allow them to need fine tuning include memories, phase locked loops, and high
address both the financial and technical challenges of process speed I/Os. They are prime candidates for testing at this stage.
migration.
One of the most important moves that design teams can make is
to adopt a methodology of verifying blocks in silicon using test
chips early and often during the design. Altera adopted this
approach for the 90 nm generation and has carried it over to the
65 nm and 40nm generations to achieve high success with first
production silicon. The approach supports design reuse to save
development cost as well as helping in understanding and Trial Plot #1=37 Dopant Atoms Trial Plot #2 = 45 Dopant Atoms Trial Plot #3 = 60 Dopant Atoms
resolving new process design challenges. Figure 2. Trial Plot Diagrams showing a random distribution of
doping atoms in a 45-nm transistor channel
Test before you buy
Test chips help address numerous design issues by validating both As the design progresses, test chips allow designers to evaluate
the circuit design and process characteristics. The first test the integration of blocks into larger structures. The chips also
chips, run early in the design effort, can contain simple logic provide an opportunity to evaluate any modifications made as a
blocks and interconnects or single transistors. The design of result of earlier testing. Depending on how many test chips are
these test chips can begin before the process and simulation run during the development effort, designers may have several
models are stable, giving developers a head start on process opportunities to repair or enhance their blocks before the design
migration. These tests will help validate some design rules and gets finalised. Altera’s development efforts typically run as many
indicate where others need modification, helping ensure that the as 9 test chips during a product design, typically spaced every 3-
circuitry will perform as expected in the final design. Testing at 4 months.
this stage, however, requires design teams to work closely with
their foundry in order to understand the deep submicron issues This use of test chips greatly increase the chances for first time
that arise. success when the full design is finally fabricated, but might
appear to be a costly approach at first glance because so many
Test chips also help to account for new deep submicron effects mask sets are involved. Collaboration with the foundry as well as
that arise with a change in technology node. Sometimes these use of shared cost programs such as TSMC’s Shuttle Program
new effects become more apparent in actual circuits than they however, can keep the cost of test chips down. During process
were in simple process test structures. Then a test chip behaves development, for instance, the foundry must run numerous test
unexpectedly, undertaking a correlation exercise can help wafers to fully characterise and tune their fabrication methods.
identify effects not previously understood. Test chips can also They also run test wafers periodically to monitor the process. A
identify circuit sensitivity to effects that were known but not fully close working relationship with the foundry provides
appreciated. opportunities to “piggy back” simple test structures on the
foundry’s wafers in the early stages a design. The Shuttle and
Later in the design process, when all effects are known and similar programs allow testing of larger structures or even full
design rules are more stable, test chips allow designers to designs. A 3.0mm by 4.0mm die size in a 40nm shuttle costs less
evaluate larger blocks. At this stage teams also can try simple than 5% of a full mask set, allowing several iterations of the
www.euroasiasemiconductor.com October 2008
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