COVER STORY
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technological difficulties tightly linked to the respective chosen walls can be incorporated within the die layout. Silex TSI
technology. Typical issues with metal based vias have been the technology consists of a through wafer trench created by DRIE
thermal incompatibility with silicon causing micro cracks and that is filled with an isolating dielectric. If the TSI technology is
reliability issues. Furthermore, a metal via must always be applied to a highly doped Si wafer, a closed vertical trench
incorporated towards the end of a MEMS process as the thermal around a “plug” of Si will constitute an isolated electrical
budget of most metal candidates would not allow too much of connection, or a through silicon via. The technology can also be
high temperature post processing. Another quite common incorporated into the handle side of an SOI wafer, allowing a
approach has been to use doped polysilicon for the through wafer highly doped handle wafer and a low doped device layer.
connection. Some of the inherent problems of such approach is to
get high enough level of dopants to accumulate during the filling The “via first” approach in this interconnect technology enables
of the via hole. Due to the low yield and very high via resistance integration of interconnect functions in sensors, actuators and
of such process, it has not reached commercial viability. microfluidic devices, as well as unrestricted integration of
MEMS and CMOS. A number of Silex customers are already
In response to customer demand for through silicon interconnect integrating the standard via process into their MEMS designs in
functionality, Silex engineers realised an idea to isolate a section order to solve interconnect and packaging issues inherent in the
of a low resistivity silicon wafer laterally by incorporating a commercialisation process of MEMS. The high temperature
trench filled with an isolating material. This isolating trench formation process and “via first” approach also enables building
most often has the shape of a square or a circle but could also CMOS sensors on top of via substrates, thereby facilitating the
take other shapes if necessary as long as it constitutes a closed integration and interconnect of MEMS and CMOS.
loop. The process begins with the formation of a through silicon
trench using a DRIE process, achieving the necessary high In developing this process Silex began to see opportunities in the
aspect ratio features in up to 600 µm thick substrates. Typical semiconductor industry that was seeking interconnect and
trench width is in the order of 10 to 20 µm. Following the trench packaging technology solutions to help integrate mixed signal
processors. One unexpected successful implementation of the via
technology is for the purpose of reducing crosstalk in mixed
signal devices such as mixed signal IC’s and combined systems
incorporating MEMS sensors and read out ASIC’s.
Although the opportunity for Silex technology to be used in
semiconductor manufacturing, the company has no desire to
deviate from their pure MEMS foundry position. Some IC
manufacturers may wish Silex to provide fabrication solutions
but the company predominately expects to licence the technology
they have christened Zero Crosstalk for IC manufacturing. Silex
may also offer licensing agreements and technology transfer
programmes to selected customers and partners who would
favour to incorporate the technology in their own existing
Schematic of a partial cross section of a device manufacturing lines.
integrating the zero cross talk process shown in blue.
The Zero Crosstalk feature originated in a design element for a
etch process, the wafer is subject to a high temperature filling of low pitch through silicon via. A via layout with pitch in the order
the trenches by a dielectric material isolating the via plugs from of 50µm between each interconnect requires each adjacent TSV
the bulk of the wafer. to share the same isolating trench. In essence the element
became a chain of isolated through silicon interconnects. The
In order to protect know how and proprietary development chain could then be laid out in the die to constitute a closed loop,
processes, Silex operates under a high level of confidentiality. confining a closed area within the loop that is electrically
Silex applies for patent protection for some of its processes as isolated from the rest of the die. No additional alterations were
they are developed. The reason for this is to secure Silex’ right to necessary to achieve the add on feature and both the TSV and
utilise the technology. Patent protection is used to prevent others the Zero Crosstalk feature are formed at the same time
supported by a corresponding patent from prohibiting Silex from providing a novel solution for manufacturers struggling to deal
using the technology in question as well as developing with the noise between digital and analogue devices that can
commercially licensed processes. The via process developed by occur and impacts negatively on the completed device. The name
Silex virtually takes care of one of the inherent, most significant of the Silex process, Zero Crosstalk provides all the clues as to
problems associated with MEMS by providing true wafer level how effective they believe their solution to be.
packaging of MEMS.
Silex strives to be one of the most advanced and efficient
Many MEMS products comprise a combination of analogue and foundries in the MEMS industry working together with
digital signal processing. Typical sensor readout for MEMS customers to give them the benefits and advantages offered by
sensors is of analogue type but also incorporates digital signal MEMS technology. They have extensive knowledge of MEMS
processing, taking place in an ASIC. In many cases, the system processing and production technology and will incorporate this
will be sensitive to signal contamination between the analogue knowledge into the new 8” wafer facility. This historical
and digital side of the system. Silex Through Silicon Insulator knowledge is the key to their ability to serve customers and
(TSI) technology is applied to create vertical walls, separating contribute to making their products successful. With several
certain regions of an IC chip or MEMS die in order to reduce foundry customers using their different via technologies today
signal contamination and crosstalk. Even pure IC’s with mixed and an line up of potential users, Silex intends making this
signal processing will benefit from the technology as the isolating process a standard in the MEMS industry.
October 2008 www.euroasiasemiconductor.com
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