Etch
High temperature
control of platinum
Platinum is being used as an alloy with nickel to help control nickel
salicide migration into silicon. Platinum is not easy to remove with
traditional etchants creating a challenge for CMOS manufacturers.
Bruno Imbert and Stephane Zoll of ST Microelectronics at Crolles,
Issue III 2009
France and Carlos Morote and Jeffery W. Butterbaugh of FSI
square4
International discuss a potential solution.
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ource/drain and polysilicon gate The manufacturing process for self aligned
oasiasemiconductor
self aligned silicide formation silicides (often referred to as salicide process)
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continues to be an important makes use of a dielectric spacer composed of
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manufacturing process for deposited silicon nitride and/or deposited
advanced CMOS integration. silicon oxide formed on the sidewall of the
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Employing nickel platinum (NiPt) alloys for gate electrode/gate dielectric stack. This
silicide formation has extended the effectiveness spacer is usually already in place and
of the salicide process into the 45 nm and 32nm used for self aligning the source/drain
generations. The use of platinum and the need implants to the gate edge.
for reduced formation anneal temperatures, After all of the source/drain
however, has created a post anneal process implants have been completed, an
challenge for selectively removing unreacted Pt. HF last cleaning process is used to
While standard HCl based chemistries can remove surface oxides and then
remove the unreacted Pt, this approach appears the metal film corresponding to
to cause oxidation of the Ni-rich phase of silicide the desired silicide is deposited
left after lower temperature formation anneals. over the entire wafer surface.
We refer to this previously unseen oxidation Usually, a capping layer of TiN is
phenomenon as parasitic oxidation. Standard deposited over the metal film to
SPM based removal chemistries do not cause protect the metal film from
parasitic oxidation, but are unable to completely oxidation and from nitridation
remove unreacted Pt. A new, high temperature during annealing steps. After
SPM based removal process, can effectively metal deposition, an annealing step
remove unreacted Pt without causing parasitic is performed which causes the
oxidation, thus extending the use of the Ni(Pt) deposited metal to react to form a metal
salicide process into future CMOS generations. silicide layer where it is in contact with single
This article discusses the need for platinum crystalline or poly crystalline silicon. After
in the silicide integration process at the 45 and silicide formation, the capping layer and
32nm design nodes, the process challenges this
entails and the parasitic oxidation problems that
arise using chlorine based chemistries for Pt
removal. It then describes the new high
temperature SPM based clean process, Figure 1 - Schematic
demonstrating its effectiveness in removing representation of a
unreacted Pt after the formation annealing CMOS transistor after
process. silicide process
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