Yield Management
Sidewall Void Defect Mechanism
Metal sidewall voids are typically caused by
corrosion. Since gross corrosion can cause
serious yield and reliability issues, metal etch
and post etch cleaning process parameters and
chemistries are carefully optimized to prevent
corrosion.
2,3,4
While sidewall void formation
usually results from plasma etch chamber or post
etch clean process abnormalities,
2
other
mechanisms may be responsible for sidewall
void formation. Hynix engineers designed a
series of experiments to determine the root
cause of sidewall void defect formation.
Setting up inspections at metal 1 and metal
2 etch (fig 2) significantly shortened the
engineering feedback loop, allowing the
engineers to quickly determine which production
factors were contributing to sidewall void
Figure 2. Puma 9150 uncovered periodic reliability failures on DRAM formation.
inspection results from devices. To determine the cause of the reliability Experimental testing eliminated etch and
a metal 1 etch layer, issue, detailed failure analysis was performed. post etch clean process conditions and
demonstrating Packaging testing linked the reliability failures to chemistries as the cause of sidewall void
capture of sidewall the back end metal layers. Isolating and cross formation. Airborne molecular contamination
void defects sectioning using focused ion beam (FIB) allowed (AMC), such as water vapour and molecular
14
the failing sites to be imaged using transmission acids, has been shown to cause metal
electron microscopy (TEM) or scanning electron corrosion.
4,7
Hynix engineers believed that
www
microscopy (SEM). These failure analysis exposure to corrosive AMCs in the fab
.eur techniques revealed that voids along the environment following metal etch caused
oasiasemiconductor
sidewalls of the metal lines (figure 1) were gradual degradation of the metal lines, leading
responsible for the reliability problems. to increased numbers of sidewall voids over
Further investigation demonstrated that the time, and ultimately poor device reliability.
reliability issue was related only to extensive Engineers performed controlled accelerated
occurrences of large voids. Small, isolated tests where wafers were placed in a chamber
sidewall voids did not affect reliability. This result with high humidity and varying chemical
.com
is consistent with early studies of the failure conditions. The corrosion progress on the test
mechanism of aluminium lines.
1
wafers could be measured as a function of
square4
Issue III 2009
Figure 3. Sidewall void
size and severity
increases with the
amount of time
between metal etch
and subsequent
processing steps
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