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understanding. With the adoption of stress engineering, oxidation, deposition, etching,
engineering as a key component of the new and annealing for dopant activation. The
device architectures, modelling of the front structure is generated by Sentaurus Process
end stress and associated stress tool. Figure 2 shows the stress distribution
enhancement of mobility has become of 3 dimensional device structure obtained
increasingly important for scaling of CMOS from Sentaurus Process simulation.
devices. The sources of stress in silicon Simulated DC and RF characteristics for
technology come from a variety of strain process induced strained Si (PSS) n and p
generated by different processes such as MOSFETs are presented below. Figure 3
oxidation, thermal mismatch, intrinsic shows the Id Vd characteristics of the 45nm
stress, and dopants. Stress modelling is MOSFETs with and without strained Si
becoming a very important part of the channel. For the n MOSFETs, the simulated
simulation methodology needed to help results indicate an approximately 23%
evaluate and engineer improved device increase in drain current at Vds = Vgs= 1.2
performance due to stress. However, it must V due to an enhancement in electron
be used along with calibrated process mobility as a result of the strain in the
simulation for doping profiles and a device channel. For the p MOSFETs, a whole
simulator that correctly models the change mobility enhancement ratio of 1.5 times that
in device characteristics due to stress. of bulk silicon is used. The resulting
simulation demonstrates an approximately
TCAD has the power to analyse accurately 17% enhancement of drain current with Figure 5. Parallel co-ordinate plot. The
the impact of process parameter variations respect to the conventional silicon p process is optimised with respect to
on device characteristics and may be used MOSFETs. The bias dependence of fT is stress, threshold voltage, current, and
to address and control process variability as shown in Figure 4. It is interesting to transconductance
needed for modelling the manufacturing note that TCAD simulation predicts the fT
process. In process modelling, a systematic of n and p MOSFETs of about 470 and Conclusion
design of experiments (DoE) run is 180GHz. Currently, strained Si is the performance
performed. DoE experiments can be booster for extending Moore’s law. Local
systematically set up, with control over Process variability has become a primary strain approach towards strained Si
process parameters and arbitrary choice of concern with regard to manufacturability engineering perhaps would be the simplest
device performance characteristics. and yield. As device dimensions shrink, among the possible approaches. However,
the sensitivity of device performance to scaling issues of local strain approach may
The models developed from DoE are known process variation also increases. With 45 nm require wafer level uniaxial strain to provide
as process compact models (PCMs). They processes, it is imperative to develop a most of the total strain for future device
are analogous to compact models for systematic TCAD based methodology to generations. It is now believed that wafer
semiconductor devices and circuits. PCM design, characterise, and optimise scale strained Si will be as effective as SOI
may be used to capture the nonlinear manufacturability to increase yield. Some in terms of extending CMOS. A
behaviour and multi parameter interactions results of the Process Compact Modelling multidisciplinary effort is required to work
of manufacturing processes. (PCM) studies via the variation of on novel CMOS structures in the fields of
technological parameters for the (a) growth and fabrication of novel substrate
optimisation of strain engineered structures materials, (b) device fabrication, (c)
In the following, simulation results of a are presented in Figure 5. The process characterisation, and (d) modelling. It will
systematic TCAD based study towards is optimised with respect to Stress, offer a perspective from characteristics of
design and optimization of strain engineered threshold voltage, current, and the new materials to device performance.
MOSFETs in 45 nm technology node using transconductance. This is illustrated in With extreme scaling down of MOSFETs in
Sentaurus TCAD tools are presented. Figure 5 using a parallel co-ordinate plot. high volume manufacturing, it is imperative
Sentaurus Process tool is used to simulate The process conditions satisfying the to develop a TCAD based methodology to
and optimise a typical 45 nm process flow, specifications are indicated in red in the design, characterise, and optimise
including channel, halo, source/drain (S/D) parallel co-ordinate plot. manufacturability to increase yield.
28 www.semiconductor-india.com | Summer 2008
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