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For process engineers, the key tool is the
process compact model (PCM) which
provides recipes to meet performance
specifications in the face of process
variations and dopant fluctuations. TCAD
applications also include technology and
design rule development, extraction of
compact models and more generally design
for manufacturability (DFM). However, to
continue to be that useful for the 32 nm
technology node and beyond, the
capabilities of TCAD have to follow the
paradigm shifts to processes and materials
considered for such nanodevices.
While introducing new structure innovations
has always been an important part of device
scaling, the integration of new materials is
facing serious hurdles in order to meet the Figure 2. 3 dimensional device structure of 45 nm devices obtained from Sentaurus
aggressive specifications of the International Process simulation (a) p-MOSFET and (b) n-MOSFET
Technology Roadmap for Semiconductors
(ITRS). Although the idea of using silicon Scaling and Non-Classical
germanium (SiGe) and silicon strained layer MOSFET Structures
epitaxy toward band gap engineering in For more than two decades the rapid
semiconductor devices is an old one, this progress in complementary metal oxide
concept has become a reality only during semiconductor (CMOS) technology was
Although the idea
the last two decades. The purpose of this accompanied by a tremendous pace of
of using silicon
article is to survey the R&D strategy and scaling, leading to an enormous increase of
address the research needs associated with the speed and functionality of electronic
germanium (SiGe)
the front end aspects of extending CMOS devices. It is now becoming increasingly
technology via strain engineering. difficult to meet MOSFET performance and silicon strained
gains with reasonable device leakage. Now
In this article, the reader is first introduced the gate leakage current constitutes a
layer epitaxy toward
with a short but versatile history of strain significant portion of the power budget of
bandgap engineering
engineering in CMOS technology. After microprocessors. Another critical scaling
reviewing the most important global and issue involves the increase of the source
in semiconductor
local strain techniques, several state of the drain series resistance resulting from the
art technologies are outlined and the need for ultra shallow p-n junctions in the
devices is an old one,
technology CAD (TCAD) modelling of source drain region. To keep the source
this concept has
strain engineered MOSFETs in process drain series resistance at a reasonable
induced strain technologies will be fraction of the total channel resistance
become a reality only
explained. Some results of a systematic (approximately10%), several alternative
study taken up (based on Technology MOSFET structures have been proposed, during the last
CAD) for the design and virtual wafer such as non overlapped gate structures,
fabrication (VWF) of strain engineered which do not require ultra shallow source
two decades
MOSFETs in Si CMOS technology are drain junctions or structures with metallic
presented. source and drain electrodes to minimise the
24 www.semiconductor-india.com | Summer 2008
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