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series resistance. Advanced multi gate it improves device performance without substrates. The approach depends largely on
structures, such as FinFETs and ultra thin device scaling. However, continued materials engineering, rather than device
body (UTB) MOSFETs might provide a miniaturisation increases device complexity design. This approach stretches the silicon
path to scaling CMOS to the end of the and internal mechanical stress. lattice by about 1%. For strained Si, a
ITRS roadmap. Strain engineering is a key graded layer of silicon germanium is grown
element in current CMOS technologies and Substrate Engineering on top of a bulk silicon wafer. A typically 2
can accommodate non classical CMOS An engineered substrate is a material that µm thick SiGe layer has a 20% germanium
structures. Extension of CMOS to 22 nm can be fabricated and introduced in the concentration, with a higher concentration
node and beyond may require new conventional silicon manufacturing, of germanium atoms at the top. Then a
nonclassical MOSFET structures coupled resulting in products that are unique and relatively thin layer of silicon, about 20 nm
with advanced materials and processes. could not have been fabricated using only thick, is placed on top of the SiGe layer.
Classes of new materials include high-k silicon substrate. The introduction of strain Over the past few years the technology to
gate dielectrics, metal and midgap gate changes the mechanical, electrical (band grow graded SiGe layers has matured.
metal electrodes, strained Si and silicon structure and mobility), and chemical
germanium alloys. (diffusion and activation) properties of a Strained Si in which the SiGe layer is
semiconductor. The various effects of stress bonded to an insulating substrate, generally
These new materials will lower the gate and strain on silicon and silicon technology known as SiGe on insulator (SGOI)
leakage current and gate resistance and have been studied since the 1950s. Most technology is now available. Strained
reduce the polygate electrode depletion significant to silicon technology are the silicon, while promising, faces several key
capacitance, and increase the device speed. changes in band gap, effective mass, challenges. Minimising the number of
Nonclassical CMOS structures offer better mobility, diffusivity of dopants, and dislocations within the silicon will be
control of short channel effects, improved oxidation rates. The strain effects on important to keeping yield rates high.
Ion via higher channel mobility, lower load mobility were found to be anisotropic and Maintaining the level of strain during the
capacitance and lower propagation delay carrier effects were found to be different for manufacturing process is another challenge.
time. As we enter the nanometre regime, bulk silicon and inversion layers. Also a major drawback common to all
stress from standard process steps such as global strain techniques for CMOS
source/drain doping introduce significant A classification of strain techniques technology is that they can provide only one
stress in the channel of MOSFETs. With the currently in use may be made in two main type of strain.
continuing reduction of device dimensions, categories. Strain is introduced across the
the impact of process induced stress on entire substrate in global strain techniques, “Local” strained Si technology is
device performance is becoming whereas local techniques induce strain in incorporated during the transistor
increasingly important. Besides scaling, selected regions of the wafer. Some of the fabrication process. The strains induced
several innovative mobility enhancement most important strain technologies that are during transistor processing are typically
techniques are being attempted to maintain currently used in industry are given in uniaxial (i.e., in one direction) and are
the CMOS performance improvement. Figure 1. A key challenge of all incorporated via tensile/compressive
Mobility enhancement is attractive because technologies is their ability to be integrated capping layers or recessed epitaxial film
into the CMOS manufacturing processes deposition in the source drain regions.
and to avoid significant increase in These processes are generally not universal
processing costs. in their implementation and need to be
tailored to a particular transistor integration
Global vs. local strain scheme. The straining technique based on
At present, in CMOS transistor engineering, process is known as process induced strain
mainly two approaches are being used in where stress is induced in a specified zone
obtaining the desired strain. One is based on or ‘local’ in the transistor. Local strain
developing the strain at the substrate level approach has currently turned out to be
before the transistor is built. This is known more promising in CMOS technology and
Figure 3. Simulated Id Vd characteristics as the ‘global’ approach, for example, is the first strain technologies used in high
with mobility enhancement due to strain strained Si on relaxed SiGe virtual volume production. However, the drawback
26 www.semiconductor-india.com | Summer 2008
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