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of process induced strain techniques is their principle, three kinds of stresses can be
strong device geometry dependence, applied to the transistor: (a) uniaxial stress
making their scaling behaviour less along one crystallographic direction, (b)
predictable. The following CMOS process biaxial stress along two perpendicular
steps are mainly responsible for stress in the crystallographic directions, and (c)
transistor channel: hydrostatic stress applied uniformly in all
xrhombus Shallow trench isolation (STI) three directions.
xrhombus silicidation at the source/drain region
xrhombus nitride contact etch stop liners (CESL) Hybrid Orientation
Technology
The local strain techniques have the Besides substrate induced and process Figure 4. Cut off frequency (fT) as a
following advantages; (i) strain can be induced stress engineering, wafer substrate function of gate bias for 45 nm PSS p
tailored to optimise performance for both n orientation and channel orientation can and n MOSFETs
channel and p channel MOSFETs, (ii) the improve mobility. Different surface
threshold voltage shift is smaller in orientation and direction of applied field for generation microelectronics. The ultimate
uniaxially stressed MOSFETs, (iii) the different in plane stress provide different advantage of working with Ge is the carrier
stress memorisation technique (SMT), and interaction with carrier transport. The mobility enhancement, making it attractive
(iv) local stress techniques are cheaper and hybrid orientation technology (HOT) for high speed circuit applications. Low
compatible with standard CMOS. combines different silicon substrate field electron mobility in Ge is more than
orientations and channel directions on the double that of Si (3900 vs. 1500 cm2/V-s)
Starting from the 90 nm node, companies same wafer and can be used in conjunction and the increase is four fold for holes (1900
such as IBM, Intel, Texas Instruments, and with strain techniques. Since strain yields an vs. 450 cm2/V-s).
Freescale have incorporated the selective anisotropic mobility, the proper channel
epitaxial growth technique to transfer direction and substrate orientation have Despite the intrinsic speed advantages of
uniaxial compressive stress into the Si to be chosen to obtain the maximum implementing Ge transistor technology, Ge
channel by growing a local epitaxial film of mobility enhancement. has not established a strong presence as an
SiGe in the source and drain region of p electronic material for ubiquitous
channel MOSFETs. Depending on the In the hybrid orientation technology, which microelectronic application because it does
proximity of the SiGe to the channel and is based on wafer bonding techniques and not form a stable oxide, which is critical for
the Ge content, 500-900 MPa stress is selective epitaxy, the larger carrier mobility gate electrode formation, limiting its utility
created in the channel. Using this technique of holes for (110) oriented substrate is in traditional MOS manufacturing methods.
impressive saturation drain current exploited to enhance the performance of p
enhancement up to 20%-25% has been channel MOSFETs. HOT seems promising Strain engineered MOSFETs:
demonstrated for p channel MOSFETs. A because processes are directly compatible Modelling and Simulation
tensile Si nitride capping layer is used to with existing CMOS technology and strain Although strain engineering is getting
introduce tensile uniaxial strain into the n engineering. increasing emphasis in CMOS technology,
channel MOSFET, which enhanced the the maximum performance enhancement
drive current by 10%. A combination of Strained Ge obtainable is still not known. It is
global and local approaches is also feasible Transistors with pure Ge channels are being convenient to use TCAD simulations with
and presently under active investigation. In investigated for implementation in next accurate physical models to gain a better
Transistors with pure Ge channels are being investigated for
implementation in next generation microelectronics. The ultimate
advantage of working with Ge is the carrier mobility enhancement,
making it attractive for high speed circuit applications
Summer 2008 | www.semiconductor-india.com 27
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