INDIA Institute of Technology vFINAL DR 17/6/08 09:13 Page 23
Semiconductor India
Strain engineered MOSFETs
Much discussion on India’s
IN THE FIELD of microelectronics, the The concept of strained Si basically relies
ability to develop IC
planar Si metal oxide semiconductor field on an alteration of the equilibrium lattice
manufacturing. Many
effect transistor (MOSFET) is perhaps the constant of Si through externally applied
most important invention. It started in 1928 stress. Due to the modified lattice constant,
people seem to believe this
when J. E. Lilienfeld proposed the concept the electronic band structure of Si is
is new territory for the of field effect conductivity modulation and changed resulting in superior electronic
area. In fact India has a
the MOSFET. With the discovery of silicon properties. More specifically, the carrier
strong history of research
dioxide SiO
2
passivation for the Si mobilities are enhanced with the mobility
semiconductor system by Atalla in 1958, enhancement being a strong function of the
in the field. C. K. Maiti, T.
the modern Si MOSFET era started. Since magnitude and the direction in which the
K. Maiti and S. S. Mahato
then MOSFET performance has improved crystal is stressed. The semiconductor
from the Department of at a dramatic rate due to gate length scaling industry has now adopted strain engineering
Electronics and ECE at IIT
and has become the dominant technology for the development of integrated CMOS.
Kharagpur discuss their
for integrated circuits. However, the CMOS Strain engineering has become a critical
scaling is now approaching the fundamental feature in CMOS as it increases the drain
work on strained
limits. The huge costs of scaling CMOS current without reducing channel length.
engineered MOSFETs
devices according to Moore’s law have left
now the silicon industry at a crossroad. In Technology Modelling and Simulation
order to improve the speed of VLSI/ULSI covers the region of the semiconductor
circuits, new materials and device structures process modelling called TCAD, and it is
are being proposed. Also a major issue for one of the few enabling methodologies that
the device designers is to achieve can reduce development cycle times and
symmetrical electrical operation from costs. Statistical fluctuations inherent in any
equivalently sized n and p MOSFETs for IC manufacturing process cause variations
increased packing density in CMOS in device and circuit performance. Thus,
circuits. With the 90 nm technology node product yield and manufacturing problems
strain techniques have been introduced to necessitate costly redesign cycles.
Figure 1. Some of the most important efficiently increase the transistor drive Technology computer aided design (TCAD)
strain technologies being currently used current by enhancing the mobility of is an indispensable tool for optimisation of
in industry carriers in the channel. new generations of electronic devices in
industrial environments.
TCAD simulations allow one to explore
new technologies and novel devices through
physics based modelling, optimise process
and device performance, and control
manufacturing processes through statistical
modelling, and all on a computer and are
known as virtual wafer fabrication (VWF).
TCAD is currently being used for design,
manufacturing and yield improvement.
Summer 2008 | www.semiconductor-india.com 23
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