Test and Measurement
indicative of dynamic performance.
Both types of C-V testing are often
required.
Basic test setup
Figure 3 is the block diagramme of a
basic C-V measurement setup. Because
C-V measurements are actually made at
AC frequencies, the capacitance for the
device under test (DUT) is calculated
with the following:
Issue I 2009
C = I / 2
square4
πfV , where
DUT DUT DUT ac
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I is the magnitude of the AC
DUT
current through the DUT,
f is the test frequency, and
Figure 2. DC bias sweep of MOSCAP structure obtained during C-V testing V
ac
is the magnitude and phase
angle of the measured AC voltage
In other words, the test measures
while making the measurements with an majority carriers can be derived. The the AC impedance of the DUT by
oasiasemiconductor
AC signal (Figure 1). Commonly, AC same basic concepts apply to MOSFET applying an AC voltage and measuring
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frequencies from about 10kHz to transistors, even though their physical the resulting AC current, the AC
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10MHz are used for these types of structure and doping is more complex. voltage and the impedance phase angle
measurements. The bias is applied as a Many other parameters can be between the two.
19
DC voltage sweep that drives the derived from the three regions shown in These measurements take into
MOSCAP structure from its Figure 2 as the bias voltage is swept account series and parallel resistance
accumulation region and then into the through them. Different AC signal associated with the capacitance, as well
depletion region, and then into frequencies can reveal additional as the dissipation factor (leakage).
inversion (Figure 2). details. Low frequencies reveal what are Figure 4 (next page) illustrates the basic
A strong DC bias causes majority called quasistatic characteristics, circuit variables that can be derived
carriers in the substrate to accumulate whereas high frequency testing is more from the measurements.
near the insulator interface. Since they
can’t get through the insulating layer,
capacitance is at a maximum in the
accumulation region as the charges
stack up near that interface (i.e. d is at a
minimum). See Figure 1 as an example.
One of the fundamental parameters
that can be derived from C-V
accumulation measurements is the
silicon dioxide thickness.
As bias voltage is decreased,
majority carriers get pushed away from
the oxide interface and the depletion
region forms. When the bias voltage is
reversed, charge carriers move the
greatest distance from the oxide layer,
and capacitance is at a minimum (i.e., d
is at a maximum). From this inversion
region capacitance, the number of
Right: Figure 3. Basic test setup for
C-V measurements
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