Inspection
patterned short flow wafers utilizing 45nm
technology. Both a standard chuck and
modified chuck were evaluated, with the
modified chuck also undergoing an additional
dechuck-plasma (DP) process step during wafer
dechucking.
The SPDI technique was used to provide a
fast, absolute measurement and visualization of
process induced charging—and thus a direct
comparison between the different dechuck
procedures—immediately after wafer processing.
SPDI charge maps (Figure 5) demonstrated that
the high charge gradient of up to -900 V
associated with the incoming resist-coated
reference wafer decreased significantly after RIE
processing.
The dechucking of both standard (Chuck I)
and modified (Chuck II) chucks without
additional dechuck-plasma resulted in 12-13 V of
residual charge gradient. When an additional
dechuck-plasma step was performed on Chuck
II, the gradient was reduced still further, to a
22
range of 4V, with a more uniform signature
devoid of the charging “hot spots” seen on the
www
non-dechuck-plasma wafers.
.eur NVDs, such as metallic contamination,
oasiasemiconductor
organic contamination and process-induced
charging, occur primarily at cleaning and surface
preparation steps—the most repeated steps in
Figure 5. SPDI charge Dechucking induced charging the fab. NVDs cannot be detected by optical
maps of non-RIE An application experiment involving inspection techniques. Thus, the introduction of
processed reference GlobalFoundries investigated the level of new materials and processes in advanced
.com
wafer and wafers after residual charges after reactive ion etching (RIE) devices calls for yield management strategies
RIE processing using using different wafer dechuck processes
8
. RIE that incorporate NVD inspection as well as
different electrostatic processes typically leave an electrostatic charge traditional physical inspection. Several examples
square4
Issue VI 2009
chucks and build-up on the wafer chuck. The dechuck of NVDs that have caused yield issues have been
with/without dechuck procedure is used to reduce this charge and presented.
plasma (Source: allow the wafer to be removed from the chuck. These examples illustrate how SPDI
Global Foundries) Two electrostatic chucks were evaluated for inspection can provide “new eyes” into process
optimization of the via-etch process with issues that can cause real yield loss.
REFERENCESa[1] The International Technology Roadmap for Semiconductors 2007 Edition, Yield Enhancement.
[2] R. Bryant, et al; “Novel Full Wafer Inspection Technology for Non-Visual Residue Defects”, UCPSS, 2006.
[3] R. Brun, et al; “VOC & Metallic Contaminant Control For SOI Process Monitoring”, Frontiers of Characterization and
Metrology for Nanoelectronics Conference, 2009.
[4] A. Shimazaki, “Metallic Contamination Control in Leading-Edge ULSI Manufacturing”, UCPSS, 2008.
[5] L. Gabette, et al, “Optimization of Edge Clean Using Non-Visual Defect Inspection”, SPCC, 2009.
[6] R. Schuetten, et al; “A New Surface Analysis Method for Semiconductor Manufacturing Based on Surface Potential
Measurements”, ASMC, 2009.
[7] H. Fontaine, et al, “Plastic Containers Contamination by Volatile Acids: Accumulation, Release and Transfer to Cu
Surfaces During Wafer Storage,” UCPSS, 2006.
[8] K. Hoeppner, et al; “Novel In-Line Inspection Method for Non-Visual Defects and Charging”, ASMC, 2009.
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