Transfer printing: an emerging technology for massively parallel assembly
4a
4b
5a
4c 4c
5b
Figure 5. (a) Image of a silicon target wafer
Figure 4. (a) Schematic illustration of a source wafer consisting of densely packed devices and (b) a target
populated with 2850 chips in a single transfer
substrate that is sparsely populated with transferred devices. (c) An image taken on the printer showing a source
operation and (b) an image of flexible plastic sheet
wafer following a single transfer operation and (d) an electron micrograph of the printed chips on the target
target substrate populated using the same chipset.
substrate.
The transfer yield was 100% in both cases.
placements per hour.
The second design consisted of chips
that were 167 µm x 50 µm x 5 µm. In this
case the stamp transferred a 16 x 16 array
(256 chips) per transfer operation. The
transfer printing operation was repeated
four times to fabricate a seamless 32 x 32
array of 1024 chips. Figure 6c and 6d show
electron micrographs of the printed chips.
6a 6b
The tether fracture surfaces are visible in
both Figure 6b and 6d. Figure 7 shows a
yield map for the 1024 chip array.
To measure the placement accuracy
of the printer, target wafers were prepared
with a reference pattern. In this case, 150
mm glass wafers were patterned with a
500 Å Ti layer using a lift-off process with
negative acting photoresist. A 3 µm layer
of benzocyclobutene (BCB) was applied to
the wafers before transfer printing. In this
6c 6d case, the target wafers were populated with
the 167 µm x 50 µm x 5 µm chips. Figure
Figure 6. Scanning electron micrographs of transfer printed silicon chips.
8 illustrates the metrology method used
to measure the placement accuracy. First,
acid. Following the sacrificial etch process printed onto a 100 mm silicon target wafer the camera on the printer is used to store
the photoresist was stripped. coated with a spin-on polymer. Figure images of the printed chips and metrology
In the first design, the chip dimensions 5b shows the same chips printed onto a marks. An automated routine is used to
were 450 µm x 40 µm x 5 µm. It is worth plastic sheet coated with an adhesive layer. compute and subtract the background,
noting that traditional serial assembly Figure 6a and 6b show scanning electron convert the image to black and white, and
equipment using vacuum tooling would micrographs of these 450 µm x 40 µm chips locate objects. A sort algorithm is used
face major challenges handling chips with printed onto a target silicon wafer. Using a to distinguish between chips, metrology
this form factor
2
. The transfer stamp very conservative estimate of one transfer marks and foreign objects (dust, debris).
(example shown in Figure 3) consisted operation per minute, the throughput of Finally, the chip placement accuracy (Δx,
of a 30 x 95 array of molded elastomeric the transfer printing would be in excess Δy, Δθ) can be calculated by comparing
posts. For this design, each transfer of 170,000 chips per hours. It is conser- the located centroids of the chips relative
operation prints 2850 chips. vatively estimated that future generation to the centroids of the metrology reference
Figure 5 shows two examples of 100% printers will have cycle times less than 20 marks.
transfer yield that were demonstrated. seconds per transfer print operation, and The results of performing the metrol-
Figure 5a shows the 450 µm x 40 µm chips should enable throughputs of
~
1M chip ogy can be plotted in various ways. Figure
20 – Global Solar Technology – November/December 2008
www.globalsolartechnology.com
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