Transfer printing: an emerging technology for massively parallel assembly
The transfer printing process was first to the source wafer. An image of the
developed in Professor John Rogers’ group transfer stamp is shown in Figure 3. The
at the University of Illinois. Examples of inset shows a scanning electron micro-
transfer printed semiconductor devices graph of the stamp surface (the stamp was
previously fabricated include high mobility coated with Au to prevent charging).
silicon thin film transistors (TFTs)
5-8
, GaAs The elastomeric transfer stamp is
metal-semiconductor field-effect transistors fabricated using previously described molding
(MESFETS)
9,10
and GaN high electron processes
13
. In brief, an inverse of the
mobility transistors (HEMTs)
11
. Recently, desired stamp pattern is generated using
Ahn et al. demonstrated prototype 3-D a photodefined polymer master substrate.
heterogeneous circuits fabricated by transfer The elastomer (PDMS) is cast against the
printing
7
. Semprius, a spin-out from the master substrate, cured, and then delami-
University of Illinois, is working to scale-up nated to form the stamp. The master sub-
and commercialize this newly invented strate can be reused to generate additional
transfer printing technology. transfer stamps.
The devices to be transfer printed must After the stamp is aligned and brought
first go through a process to delineate and into contact with the released devices,
Figure 2. Semprius transfer printing tool.
release them from their source wafer. This the stamp is lifted away from the source
method utilizes sacrificial release layers
underneath the device layer. In the case of
silicon devices, silicon-on-insulator (SOI)
wafers represent a convenient and readily
available source wafer
5
. For SOI, the silicon
device is delineated by etching through
the device silicon layer down to the buried
oxide layer and then removing the buried
oxide layer using a selective wet etchant.
The devices are held in place using tethers
microfabricated in the device layer. The
tethers are designed to break or cleave in a
controlled manner during transfer printing
12
.
Similar sacrificial release strategies have
been developed for many other device
materials, including gallium arsenide
(GaAs)
7,9,10
and gallium nitride (GaN)
7,11
.
Figure 1 is a schematic illustration of
Figure 3. Transfer stamp and scanning electron micrograph revealing the microstructured surface of the stamp.
the transfer printing process. First (Figure
1a), the transfer stamp is positioned over
operation. The process also allows for the
and aligned with the source wafer. This is wafer (Figure 1b) such that the devices in
source wafer material to be used in an ef-
accomplished using the custom transfer contact with the elastomeric stamp break
ficient manner. Figure 4 illustrates the “geo-
printer shown in Figure 2. The printer, free from the source wafer. The transfer
metric magnification” that transfer printing
which consists of a 6-axis (x, y, z, θz, pitch, stamp is now populated with devices. Next
enables. By appropriately designing the source
roll) motion platform, allows for the (Figure 1c), the populated stamp is aligned
wafer and stamp, it is possible to pick-up
transfer stamp to be moved relative to the to and brought into contact with the target
only one out of every “n” devices. As a
source and target substrates. In addition, substrate. Then (Figure 1d) the stamp is
result, when operated in this “step and
there is a camera positioned above the lifted from the target substrate such that
repeat” fashion, a dense array of devices
transfer stamp that independently moves the devices are transferred to the target
on the source wafer can be transferred into
(x, y, z) relative to the stamp. The transfer substrate. This transfer process is possible
sparse arrays on the target substrate.
stamp is transparent and the camera looks because the adhesion of the device to the
through the stamp to align the stamp relative elastomeric stamp is dependent on the yield & placement accuracy
peel rate of the stamp
14
. In addition to this Several studies have been performed to
kinetic control of the adhesion, a spin-on evaluate the transfer printing yield and
1e
polymer is used on the target substrate to placement accuracy. Two separate chip
enhance the yield of the printing process. designs were evaluated. In both cases, the
Next (Figure 1e), the stamp returns to starting source wafers were SOI with a 5
the source wafer and steps to the next set µm thick device silicon layer and a 1 µm
of devices. Then the stamp returns to the thick buried oxide layer. A single photo-
target substrate and prints the devices. lithography step was performed to define
The process then repeats until the target the chip and tethers. Reactive ion etching
substrate is fully populated with devices. (RIE) with SF
6
chemistry was used to etch
The transfer process is massively through the device silicon down to the buried
Figure 1e. The transfer stamp returns to the source
parallel. The transfer stamp shown in oxide layer. The buried oxide layer was
wafer and steps over to the next set of devices.
Figure 3 prints 2850 die per transfer removed using concentrated hydrofluoric
www.globalsolartechnology.com Global Solar Technology – November/December 2008 – 19
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